S25FS256S datasheet(18/154 Pages) SPANSION

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S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

Sheet

(Pre limin ar y)

Hardware Interface

Serial Peripheral Interface with Multiple Input / Output (SPI-MIO)

Many memory devices connect to their host system with separate parallel control, address, and data signals

that require a large number of signal connections and larger package size. The large number of connections

increase power consumption due to so many signals switching and the larger package increases cost.

The S25FS-S family reduces the number of signals for connection to the host system by serially transferring

all control, address, and data information over 4 to 6 signals. This reduces the cost of the memory package,

reduces signal switching power, and either reduces the host connection count or frees host connectors for

use in providing other features.

The S25FS-S family uses the industry standard single bit Serial Peripheral Interface (SPI) and also supports

optional extension commands for 2-bit (Dual) and 4-bit (Quad) wide serial transfers. This multiple width

interface is called SPI Multi-I/O or SPI-MIO.

Signal Descriptions

3.1

Input/Output Summary

Table 3.1 Signal List

Signal Name

Type

Description

SCK

Input

Serial Clock.

CS#

Input

Chip Select.

SI / IO0

I/O

Serial Input for single bit data commands or IO0 for Dual or Quad commands.

SO / IO1

I/O

Serial Output for single bit data commands. IO1 for Dual or Quad commands.

WP# / IO2

I/O

Write Protect when not in Quad Mode (CR1V[1] = 0 and SR1NV[7] = 1).

IO2 when in Quad Mode (CR1V[1] = 1).

The signal has an internal pull-up resistor and may be left unconnected in the host

system if not used for Quad commands or write protection. If write protection is enabled

by SR1NV[7] = 1 and CR1V[1] = 0, the host system is required to drive WP# high or low

during a WRR or WRAR command.

IO3 /

RESET#

I/O

IO3 in Quad-I/O mode, when Configuration Register 1 QUAD bit, CR1V[1] =1, and CS# is

low.

RESET# when enabled by CR2V[5]=1 and not in Quad-I/O mode, CR1V[1] = 0, or when

enabled in Quad Mode, CR1V[1] = 1 and CS# is high.

The signal has an internal pull-up resistor and may be left unconnected in the host

system if not used for Quad commands or RESET#.

VDD

Supply

Power Supply.

VSS

Supply

Ground.

Unused

Not Connected. No device internal signal is connected to the package connector nor is

there any future plan to use the connector for a signal. The connection may safely be

used for routing space for a signal on a Printed Circuit Board (PCB). However, any signal

connected to an NC must not have voltage levels higher than VDD.

RFU

Reserved

Reserved for Future Use. No device internal signal is currently connected to the

package connector but there is potential future use of the connector for a signal. It is

recommended to not use RFU connectors for PCB routing channels so that the PCB may

take advantage of future enhanced features in compatible footprint devices.

DNU

Reserved

Do Not Use. A device internal signal may be connected to the package connector. The

connection may be used by Spansion for test or other purposes and is not intended for

connection to any host system signal. Any DNU signal related function will be inactive

when the signal is at VIL. The signal has an internal pull-down resistor and may be left

unconnected in the host system or may be tied to VSS. Do not use these connections for

PCB signal routing channels. Do not connect any host system signal to this connection.

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