S25FS256S datasheet(86/154 Pages) SPANSION

86 / 154 page

S25FS-S Family

S25FS-S_00_04 November 6, 2013

Data

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(Pre limin ar y)

 Read latency may be zero to several SCK cycles (also referred to as dummy cycles).

 All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted

into the device with the most significant byte first. All data is transferred with the lowest address byte sent

first. Following bytes of data are sent in lowest to highest byte address order i.e. the byte address

increments.

 All attempts to read the flash memory array during a program, erase, or a write cycle (embedded

operations) are ignored. The embedded operation will continue to execute without any affect. A very

limited set of commands are accepted during an embedded operation. These are discussed in the

individual command descriptions. While a program, erase, or write operation is in progress, it is

recommended to check that the Write-In Progress (WIP) bit is 0 before issuing most commands to the

device, to ensure the new command can be accepted.

 Depending on the command, the time for execution varies. A command to read status information from an

executing command is available to determine when the command completes execution and whether the

command was successful.

 Although host software in some cases is used to directly control the SPI interface signals, the hardware

interfaces of the host system and the memory device generally handle the details of signal relationships

and timing. For this reason, signal relationships and timing are not covered in detail within this software

interface focused section of the document. Instead, the focus is on the logical sequence of bits transferred

in each command rather than the signal timing and relationships. Following are some general signal

relationship descriptions to keep in mind. For additional information on the bit level format and signal timing

relationships of commands, see Command Protocol on page 24.

– The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) - SI for single

bit wide transfers. The memory drives Serial Output (SO) for single bit read transfers. The host and

memory alternately drive the IO0-IO3 signals during Dual and Quad transfers.

– All commands begin with the host selecting the memory by driving CS# low before the first rising edge

of SCK. CS# is kept low throughout a command and when CS# is returned high the command ends.

Generally, CS# remains low for eight bit transfer multiples to transfer byte granularity information.

Some commands will not be accepted if CS# is returned high not at an 8-bit boundary.

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