VMV3 datasheet(137/212 Pages) MICROSEMI

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

2-123

1.5 V DC Core Voltage

Table 2-196 • A3PE600L Global Resource

Military-Case Conditions: TJ = 125°C, VCC = 1.425 V

Parameter

Description

–1

Std.

Units

Min.1 Max.2 Min.1 Max.2

tRCKL

Input Low Delay for Global Clock

0.82

1.07

0.97

1.26

tRCKH

Input High Delay for Global Clock

0.81

1.10

0.95

1.30

tRCKMPWH

Minimum Pulse Width High for Global Clock

tRCKMPWL

Minimum Pulse Width Low for Global Clock

tRCKSW

Maximum Skew for Global Clock

0.30

0.35

FRMAX

Maximum Frequency for Global Clock

MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating

values.

Table 2-197 • A3PE3000L Global Resource

Military-Case Conditions: TJ = 125°C, VCC = 1.425 V

Parameter

Description

–1

Std.

Units

Min.1 Max.2 Min.1 Max.2

tRCKL

Input Low Delay for Global Clock

1.62

1.87

1.90

2.20

tRCKH

Input High Delay for Global Clock

1.61

1.90

1.89

2.24