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VMV3 датащи(PDF) 51 Page - Microsemi Corporation

номер детали VMV3
подробное описание детали  Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology
PDF  212 Pages
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производитель  MICROSEMI [Microsemi Corporation]
домашняя страница  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VMV3 датащи(HTML) 51 Page - Microsemi Corporation

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Military ProASIC3/EL Low Power Flash FPGAs
Revision 3
2-37
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
Table 2-41 • I/O Short Currents IOSH/IOSL
Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only
Drive Strength
IOSL (mA)*
IOSH (mA)*
3.3 V LVTTL / 3.3V LVCMOS
2mA
25
27
4mA
25
27
6mA
51
54
8mA
51
54
12mA
103
109
16mA
103
109
3.3 V LVCMOS Wide Range
100 µA
Same specification as regular LVCMOS 3.3 V
2.5 V LVCMOS
2mA
16
18
4mA
16
18
6mA
32
37
8mA
32
37
12mA
65
74
1.8 V LVCMOS
2mA
9
11
4mA
17
22
6mA
35
44
8mA
35
44
1.5V LVCMOS
2mA
13
16
4mA
25
33
3.3 V PCI/PCI-X
Per PCI/PCI-X specification
103
109
Note:
*TJ = 100°C
Table 2-42 • Schmitt Trigger Input Hysteresis, Hysteresis Voltage Value (typical) for Schmitt Mode Input
Buffers Applicable to A3PE600L and A3PE3000L Only
Input Buffer Configuration
Hysteresis Value (typical)
3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)
240 mV
2.5 V LVCMOS (Schmitt trigger mode)
140 mV
1.8 V LVCMOS (Schmitt trigger mode)
80 mV
1.5 V LVCMOS (Schmitt trigger mode)
60 mV
1.2 V LVCMOS (Schmitt trigger mode)
40 mV



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