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VMV3 датащи(PDF) 136 Page - Microsemi Corporation |
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VMV3 датащи(HTML) 136 Page - Microsemi Corporation |
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136 / 212 page ![]() Military ProASIC3/EL DC and Switching Characteristics 2-122 Revision 3 Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-125. Table 2-194 to Table 2-197 on page 2-123 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics 1.2 V DC Core Voltage Table 2-194 • A3PE600L Global Resource Military-Case Conditions: TJ = 125°C, VCC = 1.14 V Parameter Description –1 Std. Units Min.1 Max.2 Min.1 Max.2 tRCKL Input LOW Delay for Global Clock 0.95 1.23 1.12 1.44 ns tRCKH Input HIGH Delay for Global Clock 0.94 1.26 1.10 1.48 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.32 0.38 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. Table 2-195 • A3PE3000L Global Resource Military-Case Conditions: TJ = 125°C, VCC = 1.14 V Parameter Description –1 Std. Units Min.1 Max.2 Min.1 Max.2 tRCKL Input LOW Delay for Global Clock 1.81 2.09 2.13 2.42 ns tRCKH Input HIGH Delay for Global Clock 1.80 2.13 2.12 2.45 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns tRCKMPWL Minimum Pulse Width LOW for Global Clock ns tRCKSW Maximum Skew for Global Clock 0.32 0.38 ns FRMAX Maximum Frequency for Global Clock MHz Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. |
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