VMV3 datasheet(139/212 Pages) MICROSEMI

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

2-125

Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-200 • Military ProASIC3/EL CCC/PLL Specification

For Devices Operating at 1.2 V DC Core Voltage: Applicable to A3PE600L and A3PE3000L Only

Parameter

Min.

Typ.

Max.

Units

Clock Conditioning Circuitry Input Frequency

fIN_CCC

1.5

250

MHz

Clock Conditioning Circuitry Output Frequency fOUT_CCC

0.75

250

MHz

Delay Increments in Programmable Delay Blocks 1, 2

360

Number of Programmable Values in Each Programmable Delay Block

Serial Clock (SCLK) for Dynamic PLL3

100

MHz

Input cycle-to-cycle jitter (peak magnitude)

Acquisition Time

LockControl = 0

300

µs

LockControl = 1

6.0

Tracking Jitter4

LockControl = 0

LockControl = 1

1.5

Output Duty Cycle

48.5

51.5

Delay Range in Block: Programmable Delay 1 1,2

1.2

15.65

Delay Range in Block: Programmable Delay 2 1,2

0.025

15.65

Delay Range in Block: Fixed Delay 1,2

3.5

CCC Output Peak-to-Peak Period Jitter FCCC_OUT

Max. Peak-to-Peak Period Jitter5,6

SSO

 2 SSO  4

SSO

 8

SSO

 16

0.75 MHz to 50 MHz

0.50%

0.60%

0.80%

1.60%

50 MHz to 160 MHz

2.50%

4.00%

6.00%

12.00%

Notes:

1. This delay is a function of voltage and temperature. See Table 2-5 on page 2-8 for deratings.

2. TJ = 25°C, VCC = 1.2 V.

3. Maximum value obtained for a –1 speed grade device in worst-case military conditions. For specific junction

temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge.

Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter.

5. Measurements done with LVTTL 3.3 V, 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.14V, VQ/PQ/TQ

type of packages, 20 pF load.

6. Switching I/Os are placed outside of the PLL bank.

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