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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VMV3 датащи(PDF) 133 Page - Microsemi Corporation |
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VMV3 датащи(HTML) 133 Page - Microsemi Corporation |
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133 / 212 page  Military ProASIC3/EL Low Power Flash FPGAs Revision 3 2-119 Table 2-192 • Register Delays Military-Case Conditions: TJ = 125°C, VCC = 1.425 V for A3PE600L and A3PE3000L Parameter Description –1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.58 0.69 ns tSUD Data Setup Time for the Core Register 0.45 0.53 ns tHD Data Hold Time for the Core Register 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.48 0.57 ns tHE Enable Hold Time for the Core Register 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.42 0.50 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.42 0.50 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.24 0.28 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.24 0.28 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 0.34 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 0.34 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.56 0.64 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.56 0.64 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values. |
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