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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M68ICS08GR датащи(PDF) 108 Page - Freescale Semiconductor, Inc |
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M68ICS08GR датащи(HTML) 108 Page - Freescale Semiconductor, Inc |
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108 / 408 page  Clock Generator Module (CGMC) Technical Data MC68HC908GR8 — Rev 4.0 108 Clock Generator Module (CGMC) MOTOROLA this table: 8. Select a VCO linear range multiplier, L, where fNOM = 38.4 kHz 9. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, fVRS. The center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL. For proper operation, 10. Verify the choice of P, R, N, E, and L by comparing fVCLK to fVRS and fVCLKDES. For proper operation, fVCLK must be within the application’s tolerance of fVCLKDES, and fVRS must be as close as possible to fVCLK. NOTE: Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. 11. Program the PLL registers accordingly: a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent of P. b. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E. Frequency Range E 0 < fVCLK < 9,830,400 0 9,830,400 ≤ f VCLK < 19,660,800 1 19,660,800 ≤ f VCLK < 39,321,600 2 NOTE: Do not program E to a value of 3. L round f VCLK 2 E f NOM × -------------------------- = f VRS L2 E × ()f NOM = f VRS f VCLK – f NOM 2 E × 2 -------------------------- ≤ Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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