M68ICS08GR datasheet(104/408 Pages) FREESCALE

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Clock Generator Module (CGMC)

Technical Data

MC68HC908GR8 — Rev 4.0

104

Clock Generator Module (CGMC)

MOTOROLA

frequency, fRDV. The circuit determines the mode of the PLL and the lock

condition based on this comparison.

7.4.4 Acquisition and Tracking Modes

The PLL filter is manually or automatically configurable into one of two

operating modes:

•

Acquisition mode — In acquisition mode, the filter can make large

frequency corrections to the VCO. This mode is used at PLL

startup or when the PLL has suffered a severe noise hit and the

VCO frequency is far off the desired frequency. When in

acquisition mode, the ACQ bit is clear in the PLL bandwidth control

•

Tracking mode — In tracking mode, the filter makes only small

corrections to the frequency of the VCO. PLL jitter is much lower

in tracking mode, but the response to noise is also slower. The

PLL enters tracking mode when the VCO frequency is nearly

correct, such as when the PLL is selected as the base clock

source. (See Base Clock Selector Circuit.) The PLL is

automatically in tracking mode when not in acquisition mode or

when the ACQ bit is set.

7.4.5 Manual and Automatic PLL Bandwidth Modes

The PLL can change the bandwidth or operational mode of the loop filter

manually or automatically. Automatic mode is recommended for most

users.

In automatic bandwidth control mode (AUTO = 1), the lock detector

automatically switches between acquisition and tracking modes.

Automatic bandwidth control mode also is used to determine when the

VCO clock, CGMVCLK, is safe to use as the source for the base clock,

CGMOUT. (See PLL Bandwidth Control Register.) If PLL interrupts are

enabled, the software can wait for a PLL interrupt request and then

check the LOCK bit. If interrupts are disabled, software can poll the

LOCK bit continuously (during PLL startup, usually) or at periodic

intervals. In either case, when the LOCK bit is set, the VCO clock is safe

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