OR4E2 datasheet(71/124 Pages) AGERE

71 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA Configuration Modes (continued)

5-4487(F)

Figure 45. Slave Parallel Configuration Schematic

Daisy Chaining

Multiple FPGAs can be configured by using a daisy chain of the FPGAs. Daisy chaining uses a lead FPGA and one

or more FPGAs configured in slave serial mode. The lead FPGA can be configured in any mode except slave

parallel mode.

All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on

positive CCLK and out on negative CCLK edges.

An upstream FPGA that has received the preamble and length count outputs a high on DOUT until it has received

the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After loading

and retransmitting the preamble and length count to a daisy chain of slave devices, the lead device loads its config-

uration data frames. The loading of configuration data continues after the lead device has received its configuration

data if its internal frame bit counter has not reached the length count. When the configuration RAM is full and the

number of bits received is less than the length count field, the FPGA shifts any additional data out on DOUT.

The configuration data is read into DIN of slave devices on the positive edge of CCLK, and shifted out DOUT on the

negative edge of CCLK. Figure 46 shows the connections for loading multiple FPGAs in a daisy-chain configura-

tion.

The generation of CCLK for the daisy-chained devices that are in slave serial mode differs depending on the config-

uration mode of the lead device. A master parallel mode device uses its internal timing generator to produce an

internal CCLK at eight times its memory address rate (RCLK). The asynchronous peripheral mode device outputs

eight CCLKs for each write cycle. If the lead device is configured in slave mode, CCLK must be routed to the lead

device and to all of the daisy-chained devices.

MICRO-

PROCESSOR

SYSTEM

D[7:0]

DONE

CCLK

CS1

HDC

LDC

VDD

INIT

PRGM

CS0

SERIES

FPGA

ORCA

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