OR4E2 datasheet(49/124 Pages) AGERE

49 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Embedded System Bus (ESB)

Implemented using the open standard, on-chip bus

AMBA-AHB 2.0 specification, the Series 4 devices con-

nects all the FPGA elements together with a standard-

ized bus framework. The ESB facilitates communication

among MPI, configuration, EBRs, and user logic in all

the generic FPGA devices. AHB serves the need for

high-performance SoC as well as aligning with current

synthesis design flows. Multiple bus masters optimize

system performance by sharing resources between dif-

ferent bus masters such as the MPI and configuration

logic. The wide data bus configuration of 32 bits with

4-bit parity supports the high-bandwidth of data-inten-

sive applications of using the wide on-chip memory.

AMBA enhances a reusable design methodology by

defining a common backbone for IP modules.

The ESB is a synchronous bus that is driven by either

the MPI clock, internal oscillator, CCLK (slave configu-

ration modes), TCK (JTAG configuration modes), or by

a user clock from routing. During initial configuration

and reconfiguration, the bus clock is defaulted to the

configuration clock. The postconfiguration clock source

is set during configuration. The user has the ability to

program several slaves through the user logic interface.

Embedded block RAM also interfaces seamlessly to the

AHB bus.

A single bus arbiter controls the traffic on the bus by

ensuring that only one master has access to the bus at

any time. The arbiter monitors a number of different

requests to use the bus and decides which request is

currently the highest priority. The configuration modes

have the highest priority and overrides all normal user

modes. Priority can be programmed between MPI and

user logic at configuration in generic FPGAs. If no prior-

ity is set, a round-robin approach is used by granting

the next requesting master in a rotating fixed order.

Several interfaces exist between the ESB and other

FPGA elements. The MPI interface acts as a bridge

between the external microprocessor bus and ESB.

The MPI may have different clock domains than the

ESB if the ESB clock is not sourced from the external

microprocessor clock. Pipelined operation allows high-

speed memory interface to the EBR and peripheral

access without the requirement for additional cycles on

the bus. Burst transfers allow optimal use of the mem-

ory interface by giving advance information of the

nature of the transfers.

Table 27 is a listing of the ESB register file and brief

descriptions. Table 28 shows the system interrupt regis-

ters, and Table 29 and Table 30 show the FPGA status

and command registers, all with brief descriptions.

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