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OR4E2 датащи(PDF) 17 Page - Agere Systems |
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OR4E2 датащи(HTML) 17 Page - Agere Systems |
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17 / 124 page ![]() Lucent Technologies Inc. 17 Preliminary Data Sheet December 2000 ORCA Series 4 FPGAs Programmable Logic Cells (continued) The ripple mode can be used in one of four submodes. The first of these is adder-subtractor submode. In this submode, each LUT generates three separate out- puts. One of the three outputs selects whether the carry-in is to be propagated to the carry-out of the cur- rent LUT or if the carry-out needs to be generated. If the carry-out needs to be generated, this is provided by the second LUT output. The result of this selection is placed on the carry-out signal, which is connected to the next LUT carry-in or the COUT/FCOUT signal, if it is the last LUT (K7/K3). Both of these outputs can be any equation created from KZ[1] and KZ[0], but in this case, they have been set to the propagate and gener- ate functions. The third LUT output creates the result bit for each LUT output connected to F[7:0]/F[3:0]. If an adder/subtrac- tor is needed, the control signal to select addition or subtraction is input on F5A/F5C inputs. These inputs generate the controller input AS. When AS = 0, this function performs the adder, A + B. When AS = 1, the function performs the subtractor, A – B. The result bit is created in one-half of the LUT from a single bit from each input bus KZ[1:0], along with the ripple input bit. The second submode is the counter submode (see Figure 10). The present count, which may be initialized via the PFU DIN inputs to the latches/FFs, is supplied to input KZ[0], and then output F[7:0]/F[3:0] will either be incremented by one for an up counter or decre- mented by one for a down counter. If an up/down counter is needed, the control signal to select the direc- tion (up or down) is input on F5A and F5C. When F5[A:C], respectively per nibble, is a logic 1, this indi- cates a down counter and a logic 0 indicates an up counter. 5-5756(F) Figure 10. Counter Submode F7 K7[0] K7 DQ C C DQ Q7 REGCOUT COUT F6 K6[0] K6 DQ Q6 F4 K4[0] K4 DQ Q4 F3 K3[0] K3 DQ Q3 F2 K2[0] K2 DQ Q2 F1 K1[0] K1 DQ Q1 F5 K5[0] K5 DQ Q5 F0 K0[0] K0 DQ Q0 CIN/FCIN FCOUT |
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