OR4E2 datasheet(22/124 Pages) AGERE

22 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells (continued)

As discussed in the Memory Mode section on page 19,

if the SLIC is placed into one of the modes where it

contains both buffers and a decode or AOI function

(e.g., BUF_BUF_DEC mode), the DEC output can be

gated with the 3-state input signal. This allows up to a

6-input decode (e.g., BUF_DEC_DEC mode) plus the

3-state input to control the enable/disable of up to four

buffers per SLIC. Figure 15—Figure 19 show several

configurations of the SLIC, while Table 6 shows all of

the possible modes.

Table 6. SLIC Modes

5-5744(F).a.

Figure 14. SLIC All Modes Diagram

Mode

No.

Mode

BUF

[3:0]

BUF

[7:4]

BUF

[9:8]

BUFFER

Buffer

BUF_BUF_DEC

Buffer

Decoder

BUF_DEC_BUF

Buffer

Decoder

Buffer

BUF_DEC_DEC

Buffer

Decoder Decoder

DEC_BUF_BUF Decoder

Buffer

DEC_BUF_DEC Decoder

Buffer

Decoder

DEC_DEC_BUF Decoder Decoder

Buffer

DECODER

Decoder Decoder Decoder

SIN9

SOUT09

DEC

0/1

TRI

0/1

SOUT08

SOUT07

SOUT06

SOUT05

SOUT04

SOUT03

SOUT02

SOUT01

SOUT00

LOGIC 1 OR 0

SIN8

LOGIC 1 OR 0

SIN7

LOGIC 1 OR 0

SIN6

LOGIC 1 OR 0

SIN5

LOGIC 1 OR 0

SIN4

LOGIC 1 OR 0

SIN3

LOGIC 1 OR 0

SIN2

LOGIC 1 OR 0

SIN1

LOGIC 1 OR 0

SIN0

LOGIC 1 OR 0

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