OR4E2 datasheet(65/124 Pages) AGERE

65 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA Configuration Modes (continued)

5-4456(F)

Figure 39. Master Serial Configuration Schematic

Asynchronous Peripheral Mode

Figure 40 shows the connections needed for the asynchronous peripheral mode. In this mode, the FPGA system

interface is similar to that of a microprocessor-peripheral interface. The microprocessor generates the control sig-

nals to write an 8-bit byte into the FPGA. The FPGA control inputs include active-low CS0 and active-high CS1 chip

selects and WR and RD inputs. The chip selects can be cycled or maintained at a static level during the configura-

tion cycle. Each byte of data is written into the FPGA’s D[7:0] input pins. D[7:0] of the FPGA can be connected to

D[7:0] of the microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ORCA

Foundry, then the user must mirror the bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect

D[7:0] of the FPGA to D[0:7] of the microprocessor.

The FPGA provides an RDY/BUSY status output to indicate that another byte can be loaded. A low on RDY/BUSY

indicates that the double-buffered hold/shift registers are not ready to receive data, and this pin must be monitored

to go high before another byte of data can be written. The shortest time RDY/BUSY is low occurs when a byte is

loaded into the hold register and the shift register is empty, in which case the byte is immediately transferred to the

shift register. The longest time for RDY/BUSY to remain low occurs when a byte is loaded into the holding register

and the shift register has just started shifting configuration data into configuration RAM.

The RDY/BUSY status is also available on the D7 pin by enabling the chip selects, setting WR high, and applying RD

low, where the RD input provides an output enable for the D7 pin when RD is low. The D[6:0] pins are not enabled to

drive when RD is low and, therefore, only act as input pins in asynchronous peripheral mode. Optionally, the user

can ignore the RDY/BUSY status and simply wait until the maximum time it would take for the RDY/BUSY line to go

high, indicating the FPGA is ready for more data, before writing the next data byte.

DIN

ORCA

SERIES

FPGA

CCLK

DOUT

TO DAISY-

CHAINED

DEVICES

DATA

CLK

CEO

DATA

CLK

RESET/OE

CEO

TO MORE

SERIAL ROMs

AS NEEDED

DONE

PRGM

PROGRAM

RESET/OE

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