OR4E2 datasheet(5/124 Pages) AGERE

5 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

System Features (continued)

Variable-size bused readback of configuration data capability with the built-in MPI and system bus.

Internal, 3-state, bidirectional buses with simple control provided by the SLIC.

Meets universal test and operations PHY interface for ATM (UTOPIA) Levels 1, 2, and 3. Also meets proposed

specifications for UTOPIA Level 4 for 10 Gbits/s interfaces.

New clock routing structures for global and local clocking significantly increases speed and reduces skew

(<200 ps for OR4E4).

New local clock routing structures allow creation of localized clock trees anywhere on the device.

New DDR, QDR, and ZBT memory interfaces support the latest high-speed memory interfaces.

New 2x/4x uplink and downlink I/O shift registers capabilities interface high-speed external I/Os to reduced inter-

nal logic speed.

ORCA Foundry 2000 development system software. Supported by industry-standard CAE tools for design entry,

synthesis, simulation, and timing analysis.

Table 2. System Performance

1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.

2. Implemented using two 32 x 4 RAMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.

3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (seven of 15 PFUs

contain only pipelining registers).

4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.

5. Implemented using 32 x 4 dual-port RAM mode.

6. Implemented in one partially occupied SLIC, with decoded output setup to CE in the same PLC.

7. Implemented in five partially occupied SLICs.

Function

No. PFUs

Unit

16-bit loadable up/down counter

282

MHz

16-bit accumulator

282

MHz

8 x 8 Parallel Multiplier

Multiplier mode, unpipelined 1

11.5

MHz

ROM mode, unpipelined 2

8175

MHz

Multiplier mode, pipelined 3

197

MHz

32 x 16 RAM (synchronous)

Single port, 3-state bus 4

4264

MHz

Dual-port 5

4340

MHz

128 x 8 RAM (synchronous)

Single port, 3-state bus 4

8264

MHz

Dual-port, 3-state bus 5

8264

MHz

Address Decode

8-bit internal, LUT-based

0.25

1.37

8-bit internal, SLIC-based 6

00.73

32-bit internal, LUT-based

4.68

32-bit internal, SLIC-based 7

02.08

36-bit Parity Check (internal)

4.68

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