OR4E2 datasheet(62/124 Pages) AGERE

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Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA States of Operation (continued)

Table 37. Configuration Frame Size

Devices

OR4E2

OR4E4

OR4E6

OR4E10

OR4E14

Number of Frames

1796

2436

3076

3972

4356

Data Bits/Frame

900

1284

1540

1924

2372

Maximum Configuration Data

(Number of bits/frame x Number of frames)

1,610,400

3,127,824

4,737,040

7,642,128

10,332,432

Maximum PROM Size (bits)

(add configuration header and postamble)

1,161,648

3,128,072

4,737,288

7,642,376

10,332,680

Bit Stream Error Checking

There are three different types of bit stream error

checking performed in the ORCA Series 4 FPGAs:

ID frame, frame alignment, and CRC checking.

The ID data frame is sent to a dedicated location in the

FPGA. This ID frame contains a unique code for the

device for which it was generated. This device code is

compared to the internal code of the FPGA. Any differ-

ences are flagged as an ID error. This frame is auto-

matically created by the bit stream generation program

in ORCA Foundry.

Each data and address frame in the FPGA begins with

a frame start pair of bits and ends with eight stop bits

set to 1. If any of the previous stop bits were a 0 when a

frame start pair is encountered, it is flagged as a frame

alignment error.

Error checking is also done on the FPGA for each

frame by means of a checksum byte. If an error is found

on evaluation of the checksum byte, then a checksum/

parity error is flagged. The checksum is the XOR of all

the data bytes, from the start of frame up to and includ-

ing the bytes before the checksum. It applies to the ID,

address, and data frames.

When any of the three possible errors occur, the FPGA

is forced into an idle state, forcing INIT low. The FPGA

will remain in this state until either the RESET or PRGM

pins are asserted. Also the pin CFQ_IRQ/MPI_IRQ is

forced low to signal the error and the specific type of bit

stream error is written to one of the system bus regis-

ters by the FPGA configuration logic. The PGRM bit of

the system bus control register can also be used to

reset out of the error condition and restart configura-

tion.

FPGA Configuration Modes

There are twelve methods for configuring the FPGA.

Eleven of the configuration modes are selected on the

M0, M1, and M2 inputs. The twelfth configuration mode

is accessed through the boundary-scan interface. A

fourth input, M3, is used to select the frequency of the

internal oscillator, which is the source for CCLK in

some configuration modes. The nominal frequencies of

the internal oscillator are 1.25 MHz and 10 MHz. The

1.25 MHz frequency is selected when the M3 input is

unconnected or driven to a high state.

There are three basic FPGA configuration modes:

master, slave, and peripheral. The configuration data

can be transmitted to the FPGA serially or in parallel

bytes. As a master, the FPGA provides the control sig-

nals out to strobe data in. As a slave device, a clock is

generated externally and provided into the CCLK input.

In the three peripheral modes, the FPGA acts as a

microprocessor peripheral. Table 38 lists the functions

of the configuration mode pins.

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