OR4E2 datasheet(28/124 Pages) AGERE

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Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Embedded Block RAM (continued)

CAM Mode

The CAM block is a content address memory that pro-

vides fast address searches by receiving data input

and returning addresses that contain the data. Imple-

mented in each EBR are two 16-word x 8-bit CAM

function blocks.

The CAM has three modes: single match, multiple

match, and clear, which are all achieved in one clock

cycle. In single-match mode, an 8-bit data input is inter-

nally decoded and reports a match when data is

present in a particular RAM address. Its result is

reported by a corresponding single address bit. In mul-

tiple match, the same occurs with the exception of mul-

tiple address lines report the match. Clear mode is

used to clear the CAM contents in one clock cycle by

erasing all locations.)

Arbitration logic is optionally programmed by the user

to signal occurrences of data collisions as well as to

block both ports from writing at the same time. The

arbitration logic prioritizes PORT1. When utilizing the

arbiter, the signal BUSY indicates data is being written

to PORT1. This BUSY output signals PORT1 activity by

driving a high output. The arbitration default is enabled;

however, the user may disable the arbiter in configura-

tion. If the arbiter is turned off, both ports could be writ-

ten at the same time and the data would be corrupt. In

this scenario, the BUSY signal will indicate a possible

error.

There is also a user option which dedicates PORT 1 to

communications to the system bus. In this mode, the

user logic only has access to PORT0 and arbitration

logic is enabled. The system bus utilizes the priority

given to it by the arbiter; therefore, the system bus will

always be able to write to the EBR.

Table 9. RAM Signals

Port Signals

I/O

Function

PORT 0

AR0[#:0]

Address to be read.

AW0[#:0]

Address to be written.

BW0<1:0>

Byte-write enable.

Byte = 8 bits + parity bit.

<1> = bits[17, 15:9] <0> = bits[16, 7:0]

CKR0

Positive-edge asynchronous read clock.

CKW0

Positive-edge synchronous write clock.

CSR0

Enables read to output. Active-high.

CSW0

Enables write to occur. Active-high.

D [#:0]

Input data to be written to RAM.

Q [#:0]

Output data of memory contents at referenced address.

PORT 1

AR1[#:0]

Address to be read.

AW1[#:0]

Address to be written.

BW1<1:0>

Byte-write enable.

Byte = 8 bits + parity bit.

<1> = bits[17, 15:9] <0> = bits[16, 7:0]

CKR1

Positive-edge asynchronous read clock.

CKW1

Positive-edge synchronous write clock.

CSR1

Enables read to output. Active-high.

CSW1

Enables write to occur. Active-high.

D [#:0]

Input data to be written to RAM.

Q [#:0]

Output data of memory contents at referenced address.

Control

BUSY

PORT1 writing. Active-high.

RESET

Data output registers cleared. Memory contents unaffected. Active-low.

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