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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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OR4E2 датащи(PDF) 40 Page - Agere Systems |
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OR4E2 датащи(HTML) 40 Page - Agere Systems |
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40 / 124 page  40 Lucent Technologies Inc. Preliminary Data Sheet December 2000 ORCA Series 4 FPGAs Special Function Blocks (continued) 5-6765(F) Figure 26. Boundary-Scan Interface D[7:0] INTR MICRO- PROCESSOR D[7:0] CE RA R/W DAV INT SP TMS0 TCK TDI TDO TDI TMS TCK TDO ORCA SERIES FPGA TDI ORCA SERIES FPGA TMS TCK TDO TDI TMS TCK TDO ORCA SERIES FPGA LUCENT BOUNDARY- SCAN MASTER (BSM) (DUT) (DUT) (DUT) The boundary-scan support circuit shown in Figure 26 is the 497Aa boundary-scan master (BSM). The BSM off-loads tasks from the test host to increase test throughput. To interface between the test host and the DUTs, the BSM has a general MPI and provides paral- lel-to-serial/serial-to-parallel conversion, as well as three 8K data buffers. The BSM also increases test throughput with a dedicated automatic test-pattern generator and with compression of the test response with a signature analysis register. The PC-based boundary-scan test card/software allows a user to quickly prototype a boundary-scan test setup. Boundary-Scan Instructions The Series 4 boundary-scan circuitry includes ten IEEE 1149.1, 1149.2, and 1532/D1 instructions and six ORCA-defined instructions. These also include one IEEE 1149.3 optional instruction. A 6-bit wide instruc- tion register supports all the instructions listed in Table 22. The BYPASS instruction passes data inter- nally from TDI to TDO after being clocked by TCK. Table 22. Boundary-Scan Instructions Code Instruction 000000 EXTEST 000001 SAMPLE 000011 PRELOAD 000100 RUNBIST 000101 IDCODE 000110 USERCODE 001000 ISC_ENABLE 001001 ISC_PROGRAM 001010 ISC_NOOP 001011 ISC_DISABLE 001101 ISC_PROGRAM_USERCODE 001110 ISC_READ 010001 PLC_SCAN_RING1 010010 PLC_SCAN_RING2 010011 PLC_SCAN_RING3 010100 RAM_WRITE 010101 RAM_READ 111111 BYPASS |
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