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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8945ECS/R датащи(PDF) 105 Page - Wolfson Microelectronics plc |
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WM8945ECS/R датащи(HTML) 105 Page - Wolfson Microelectronics plc |
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105 / 169 page  Production Data WM8945 w PD, May 2011, Rev 4.1 105 Figure 49 Power-On Reset Timing – DCVDD enabled first The POR ¯¯¯ signal is undefined until LDOVDD has exceeded the minimum threshold, Vpora Once this threshold has been exceeded, POR ¯¯¯ is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Once LDOVDD and DCVDD have both reached their respective power on thresholds, POR ¯¯¯ is released high, all registers are in their default state, and writes to the control interface may take place. Note that a minimum power-on reset period, TPOR, applies even if LDOVDD and DCVDD have zero rise time. (This specification is guaranteed by design rather than test.) On power down, POR ¯¯¯ is asserted low when LDOVDD or DCVDD falls below their respective power- down thresholds. Typical Power-On Reset parameters for the WM8945 are defined in Table 70. SYMBOL DESCRIPTION MIN TYP MAX UNIT Vpora Power-On undefined threshold (LDOVDD) 0.5 V Vpora_on Power-On threshold (LDOVDD) 1.15 V Vpora_off Power-Off threshold (LDOVDD) 1.12 V Vpord_on Power-On threshold (DCVDD) 0.57 V Vpord_off Power-Off threshold (DCVDD) 0.56 V TPOR Minimum Power-On Reset period 10.6 s Table 70 Typical Power-On Reset Parameters Separate Power-On Reset circuits are also implemented on the DBVDD and SPKVDD domains. These circuits ensure correct device behaviour whenever these supplies are enabled or disabled. |
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