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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8945ECS/R датащи(PDF) 102 Page - Wolfson Microelectronics plc |
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WM8945ECS/R датащи(HTML) 102 Page - Wolfson Microelectronics plc |
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102 / 169 page  WM8945 Production Data w PD, May 2011, Rev 4.1 102 Figure 47 4-Wire Readback (Open Drain) POWER MANAGEMENT The WM8945 has two control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To minimise pop or click noise, it is important to enable or disable these functions in the correct order, and to use the signal mute registers as part of a carefully structured control sequence. Refer to the “Recommended Power Up/Down Sequence” section for more details. The power management control registers are described in Table 68. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R2 (02h) Power management 1 12 INPPGAL_ENA 0 Left Input PGA Enable 0 = Disabled 1 = Enabled 10 ADCL_ENA 0 Left ADC and Record filter Enable 0 = Disabled 1 = Enabled ADCL_ENA must be set to 1 when processing left channel data from the ADC or Digital Microphone. 4 MICB_ENA 0 Microphone Bias Enable 0 = Disabled 1 = Enabled 3 BIAS_ENA 0 Master Bias Enable 0 = Disabled 1 = Enabled R3 (03h) Power management 2 14 OUTL_ENA 0 LINEOUTL enable 0 = Disabled 1 = Enabled 13 SPKR_PGA_ ENA 0 Speaker Right PGA enable 0 = Disabled 1 = Enabled 12 SPKL_PGA_ ENA 0 Speaker Left PGA enable 0 = Disabled 1 = Enabled 11 SPKR_SPKVDD _ENA 0 SPKOUTR enable 0 = Disabled 1 = Enabled Note that SPKOUTR is also controlled by SPKR_OP_ENA. When powering down SPKOUTR, the SPKR_SPKVDD_ENA bit should be reset first. |
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