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MFRC63002R датащи(PDF) 14 Page - NXP Semiconductors

номер детали MFRC63002R
подробное описание детали  Contactless reader IC
PDF  118 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

MFRC63002R датащи(HTML) 14 Page - NXP Semiconductors

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MFRC630
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.1 — 6 September 2012
227531
14 of 118
NXP Semiconductors
MFRC630
Contactless reader IC
Remark: The Most Significant Bit (MSB) has to be sent first.
8.4.2.3
Write data
To write data to the MFRC630 using the SPI interface the following byte order has to be
used. It is possible to write more than one byte by sending a single address byte
(see.8.5.2.4).
The first send byte defines both, the mode itself and the address byte.
Remark: The Most Significant Bit (MSB) has to be sent first.
8.4.2.4
Address byte
The address byte has to fulfil the following format:
The LSB bit of the first byte defines the used mode. To read data from the MFRC630 the
LSB bit is set to logic 1. To write data to the MFRC630 the LSB bit has to be cleared. The
bits 6 to 0 define the address byte.
NOTE: When writing the sequence [address byte][data1][data2][data3]..., [data1] is written
to address [address byte], [data2] is written to address [address byte + 1] and [data3] is
written to [address byte + 2].
Exception: This auto increment of the address byte is not performed if data is written to
the FIFO address
8.4.2.5
Timing Specification SPI
The timing condition for SPI interface is as follows:
Table 8.
Byte Order for MOSI and MISO
byte 0
byte 1
byte 2
3 to n-1
byte n
byte n + 1
MOSI
address 0
data 0
data 1
……..
data n
1
data n
MISO
XX
X……..
XX
Table 9.
Address byte 0 register; address MOSI
7
6
5
4
3
2
1
0
address 6
address 5
address 4
address 3
address 2
address 1
address 0
1 (read)
0 (write)
MSB
LSB
Table 10.
Timing conditions SPI
Symbol
Parameter
Min
Typ
Max
Unit
tSCKL
SCK LOW time
50
-
-
ns
tSCKH
SCK HIGH time
50
-
-
ns
th(SCKH-D)
SCK HIGH to data input hold time
25
-
-
ns
tsu(D-SCKH)
data input to SCK HIGH set-up time
25
-
-
ns
th(SCKL-Q)
SCK LOW to data output hold time
-
-
25
ns
t(SCKL-NSSH)
SCK LOW to NSS HIGH time
0
-
-
ns
tNSSH
NSS HIGH time
50
-
-
ns



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