MFRC63002R datasheet(35/118 Pages) NXP

35 / 118 page

MFRC630

All information provided in this document is subject to legal disclaimers.

Product data sheet

COMPANY PUBLIC

Rev. 3.1 — 6 September 2012

227531

35 of 118

NXP Semiconductors

MFRC630

Contactless reader IC

8.6.3.2

Block diagram

Figure 23 shows the block diagram of the receiver circuitry. The receiving process

includes several steps. First the quadrature demodulation of the carrier signal of

13.56 MHz is done. Several tuning steps in this circuit are possible.

The receiver can also be operated in a single ended mode. In this case the

Rcv_RX_single bit has to be set. In the single ended mode, the two receiver pins RXP and

RXN need to be connected together and will provide a single ended signal to the receiver

circuitry.

When using the receiver in a single ended mode the receiver sensitivity is decreased and

the achievable reading distance might be reduced, compared to the fully differential mode.

The quadrature-demodulator uses two different clocks, Q-clock and I-clock, with a phase

shift of 90

 between them. Both resulting baseband signals are amplified, filtered, digitized

and forwarded to a correlation circuitry.

The typical application is intended to implement the Fully differential mode and will deliver

maximum reader/writer distance. The Quasi differential mode can be used together with

dedicated antenna topologies that allow a reduction of matching components at the cost

of overall reading performance.

Fig 23. Block diagram of receiver circuitry

Table 21.

Configuration for single or differential receiver

Mode

rcv_rx_single

pins RXP and RXN

Fully differential

provide differential signal from

differential antenna by separate

rx-coupling branches

Quasi differential

connect RXP and RXN together

and provide single ended signal

from antenna by a single

rx-coupling branch

001aan358

13.56 MHz

I/O CLOCK

GENERATION

I-clks

Q-clks

clk_27 MHz

TIMING

GENERATION

ADC

DATA

Adc_data_ready

clk_27 MHz

mixer

mix_out_i_p

2-stage BBA

mix_out_i_n

out_i_p

out_i_n

rx_p

rx_n

rx_p

rx_n

mixer

mix_out_q_p

2-stage BBA

mix_out_q_n

out_q_p

out_q_n

rcv_gain<1:0>

rcv_hpcf<1:0>

fully/quasi-differential

rcv_gain<1:0>

rcv_hpcf<1:0>

rx_p

rx_n

MFRC63002R датащи(PDF) 35 Page - NXP Semiconductors

MFRC63002R датащи(HTML) 35 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL