MFRC63002R datasheet(60/118 Pages) NXP

60 / 118 page

MFRC630

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Product data sheet

COMPANY PUBLIC

Rev. 3.1 — 6 September 2012

227531

60 of 118

NXP Semiconductors

MFRC630

Contactless reader IC

9.4.3 FIFOLength

Number of bytes in the FIFO buffer. In 512-bit modem this register is extended by

FIFOControl.FifoLength.

9.4.4 FIFOData

In- and output of FIFO buffer. Contrary to any read/write access to other addresses,

reading or writing to the FIFO address does not increment the address pointer. Resulting

in an efficient data transfer from and to the FIFO buffer. Writing to the FIFOData register

increments, reading decrements the number of bytes present in the FIFO.

9.5 Interrupt configuration registers

The Registers IRQ0 register and IRQ1 register implement a special functionality to avoid

the not intended modification of bits.

The mechanism of changing register contents requires the following consideration:

IRQ(x). Set indicates, if a set bit on position 0 to 6 shall be cleared or set. Depending on

the content of IRQ(x).Set, a write of a logical 1 to positions 0 to 6 either clears or sets the

corresponding bit. With this register the application can modify the interrupt status which

is maintained by the MFRC630.

Bit 7 indicates, if the intended modification is a setting or clearance of a bit. Any 1 written

to a bit position 6...0 will trigger the setting or clearance of this bit as defined by bit 7.

Example: writing FFh sets all bits 6..0, writing 7Fh clears all bits 6..0 of the interrupt

request register

Table 47.

FIFOLength register (address 04h); reset value: 00h

Bit

Symbol

FIFOLength

Access

rights

Table 48.

FIFOLength bits

Bit

Symbol

Description

7 to 0

FIFOLength

Indicates the number of bytes in the FIFO buffer. In 512-bit modem this

decrements the number of bytes in the FIFO.

Table 49.

FIFOData register (address 05h);

Bit

Symbol

FIFOData

Access

rights

Table 50.

FIFOData bits

Bit

Symbol

Description

7 to 0

FIFOData

Data input and output port for the internal FIFO buffer. Refer to Section

8.5 “Buffer”.

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