MFRC63002R datasheet(7/118 Pages) NXP

7 / 118 page

MFRC630

All information provided in this document is subject to legal disclaimers.

Product data sheet

COMPANY PUBLIC

Rev. 3.1 — 6 September 2012

227531

7 of 118

NXP Semiconductors

MFRC630

Contactless reader IC

8.1 Interrupt controller

The interrupt controller handles the enabling/disabling of interrupt requests. All of the

interrupts can be configured by firmware. Additionally, the firmware has possibilities to

trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0

and IRQ1 are implemented, accompanied by two 8-bit interrupt enable registers IRQ0En

and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt

controller registers is implemented.

The MFRC630 indicates certain events by setting bit IRQ in the register Status1Reg and

additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the

host using its interrupt handling capabilities. This allows the implementation of efficient

host software.

The following table shows the available interrupt bits, the corresponding source and the

condition for its activation. The interrupt bit TimernIrq in register IRQ1 indicates an

interrupt set by the timer unit. The setting is done if the timer underflows.

The TxIrq bit in register IRq0 indicates that the transmission is finished. If the state

changes from sending data to transmitting the end of the frame pattern, the transmitter

unit sets the interrupt bit automatically.

The bit RxIrq in register IRQ0 indicates an interrupt when the end of the received data is

detected.

The bit IdleIrq in register IRQ0 is set if a command finishes and the content of the

command register changes to idle.

The waterlevel defines both - minimum and maximum warning levels - counting from top

and from bottom of the FIFO by a single value.

The bit HiAlertIrq in register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, that

means the FIFO data number has reached the top level as configured by the bit

WaterLevel.

The bit LoAlertIrq in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, that

means the FIFO data number has reached the bottom level as configured by the bit

WaterLevel.

The bit ErrIrq in register IRQ0 indicates an error detected by the contactless UART during

receive. This is indicated by any bit set to logic 1 in register Error.

The bit LPCDIrq in register IRQ0 indicates a card detected.

The bit RxSOFIrq in register IRQ0 indicates a detection of a SOF or a subcarrier by the

contactless UART during receiving.

The bit GlobalIRq in register IRQ1 indicates an interrupt occurring at any other interrupt

source when enabled.

MFRC63002R датащи(PDF) 7 Page - NXP Semiconductors

MFRC63002R датащи(HTML) 7 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL