MFRC63002R datasheet(21/118 Pages) NXP

21 / 118 page

MFRC630

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Product data sheet

COMPANY PUBLIC

Rev. 3.1 — 6 September 2012

227531

21 of 118

NXP Semiconductors

MFRC630

Contactless reader IC

Alternatively the I2C address can be configured in the EEPROM. Several address

numbers are reserved for this purpose. During device configuration, the designer has to

ensure, that no collision with these reserved addresses in the system is possible. Check

the corresponding I2C specification for a complete list of reserved addresses.

For all MFRC630 devices the upper 5 bits of the device bus address are reserved by NXP

and set to 01010(bin). The remaining 2 bits (ADR_2, ADR_1) of the slave address can be

freely configured by the customer in order to prevent collisions with other I2C devices by

using the interface pins (refer to Table 6) or the value of the I2C address EEPROM register

(refer to Table 26).

8.4.4.7

I2C-register write access

To write data from the host controller via I2C to a specific register of the MFRC630 the

following frame format shall be used.

The first byte of a frame indicates the device address according to the I2C rules. The

second byte indicates the register address followed by up to n-data bytes. In case the

address indicates the FIFO, in one frame all n-data bytes are written to the FIFO register

address. This enables for example a fast FIFO access. For any other address, the

address pointer is incremented automatically and data is written to the locations [address],

[address+1], [address+2]... [address+(n-1)]

The read/write bit shall be set to logic 0.

8.4.4.8

I2C-register read access

To read out data from a specific register address of the MFRC630 the host controller shall

use the procedure:

First a write access to the specific register address has to be performed as indicated in the

following frame:

The first byte of a frame indicates the device address according to the I2C rules. The

second byte indicates the register address. No data bytes are added.

The read/write bit shall be logic 0.

Having performed this write access, the read access starts. The host sends the device

address of the MFRC630. As an answer to this device address the MFRC630 responds

with the content of the addressed register. In one frame n-data bytes could be read using

the same register address. The address pointing to the register is incremented

automatically (exception: FIFO register address is not incremented automatically). This

enables a fast transfer of register content. The address pointer is incremented

automatically and data is read from the locations [address], [address+1], [address+2]...

[address+(n-1)]

Fig 16. First byte following the START procedure

001aam304

Bit 6

Bit 5

Bit 4

slave address

Bit 3

Bit 2

Bit 1

Bit 0

R/W

MSB

LSB

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