IMX53CEC datasheet(91/204 Pages) FREESCALE

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Electrical Characteristics

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

4.7.8.6

Synchronous Interfaces to Standard Active Matrix TFT LCD Panels

4.7.8.6.1

IPU Display Operating Signals

The IPU uses four control signals and data to operate a standard synchronous interface:

•

IPP_DISP_CLK—Clock to display

•

HSYNC—Horizontal synchronization

•

VSYNC—Vertical synchronization

•

DRDY—Active data

All synchronous display controls are generated on the base of an internally generated “local start point”.

The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.

The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved

relative to the local start point. The data bus of the synchronous interface is output direction only.

4.7.8.6.2

LCD Interface Functional Description

Figure 47 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure

signals are shown with negative polarity. The sequence of events for active matrix interface timing is:

•

DI_CLK internal DI clock, used for calculation of other controls.

•

IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).

In active mode, IPP_DISP_CLK runs continuously.

•

HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC.)

•

VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.

(Usually IPP_PIN_3 is used as VSYNC.)

•

DRDY acts like an output enable signal to the CRT display. This output enables the data to be

shifted onto the display. When disabled, the data is invalid and the trace is off.

(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)

Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels

m–1

HSYNC

VSYNC

HSYNC

LINE 1

LINE 2

LINE 3

LINE 4

LINE n-1

LINE n

DRDY

IPP_DISP_CLK

IPP_DATA

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