IMX53CEC datasheet(30/204 Pages) FREESCALE

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i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Electrical Characteristics

4.3.2

LPDDR2 I/O DC Parameters

The LPDDR2 I/O pads support DDR2/LVDDR2, LPDDR2, and DDR3 operational modes.

4.3.2.1

DDR2 Mode I/O DC Parameters

The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The

parameters in Table 12 are guaranteed per the operating ranges in Table 7, unless otherwise noted.

Low-level output current

(1.65-3.1V OVDD)

Iol

Vout = 0.2

×OVDD

Low drive

Medium drive

High drive

Max drive

2.1

4.2

6.3

8.4

——

High-Level DC input voltage1, 2

VIH

—

0.7

× OVDD

—

OVDD

Low-Level DC input voltage1, 2

VIL

—

0.3

× OVDD

Input Hysteresis

VHYS

OVDD = 1.875 V

OVDD = 2.775 V

0.25

0.34

0.45

—V

Schmitt trigger VT+2, 3

VT+

—

0.5

× OVDD

—

Schmitt trigger VT–2, 3

VT–

—

0.5

× OVDD

Input current (no pull-up/down)

Iin

Vin = OVDD or 0

—

μA

Input current (22 k

Ω Pull-up)

Iin

Vin = 0 V

Vin = OVDD

——

161

μA

Input current (47 k

Ω Pull-up)

Iin

Vin = 0 V

Vin = OVDD

——

μA

Input current (100 k

Ω Pull-up)

Iin

Vin = 0 V

Vin= OVDD

——

μA

Input current (100 k

Ω Pull-down)

Iin

Vin = 0 V

Vin = OVDD

——

μA

Keeper Circuit Resistance

—

1304

—k

1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

2 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

4 Use an off-chip pull resistor of less than 60 k

Ω to override this keeper.

Table 11. GPIO I/O DC Electrical Characteristics (continued)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

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