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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX53CEC датащи(PDF) 70 Page - Freescale Semiconductor, Inc |
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IMX53CEC датащи(HTML) 70 Page - Freescale Semiconductor, Inc |
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70 / 204 page  i.MX53xD Applications Processors for Consumer Products, Rev. 2 70 Freescale Semiconductor Electrical Characteristics 4.7.2.2 CSPI Slave Mode Timing Figure 33 depicts the timing of CSPI in slave mode. Timing characteristics were not available at the time of publication. Figure 33. CSPI/ECSPI Slave Mode Timing Diagram 4.7.2.3 ECSPI Master Mode Timing Figure 32 depicts the timing of ECSPI in master mode. Table 47 lists the ECSPI master mode timing characteristics. CS9 MISO Hold Time tHmiso 5— ns CS10 RDY to SSx Time2 tSDRY 5— ns 1 See specific I/O AC parameters Section 4.5, “I/O AC Parameters” 2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. Table 47. ECSPI Master Mode Timing Parameters ID Parameter Symbol Min Max Unit CS1 SCLK Cycle Time–Read SCLK Cycle Time–Write tclk 30 15 —ns CS2 SCLK High or Low Time–Read SCLK High or Low Time–Write tSW 14 7 —ns CS3 SCLK Rise or Fall1 tRISE/FALL —— ns CS4 SSx pulse width tCSLH Half SCLK period — ns CS5 SSx Lead Time (CS setup time) tSCS 5— ns CS6 SSx Lag Time (CS hold time) tHCS 5— ns CS7 MOSI Propagation Delay (CLOAD =20pF) tPDmosi -0.5 2.5 ns CS8 MISO Setup Time tSmiso 8.5 — ns Table 46. CSPI Master Mode Timing Parameters (continued) ID Parameter Symbol Min Max Unit CS1 CS7 CS8 CS2 CS2 CS4 CS6 CS5 CS9 SCLK SSx MISO MOSI |
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