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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX53CEC датащи(PDF) 52 Page - Freescale Semiconductor, Inc |
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IMX53CEC датащи(HTML) 52 Page - Freescale Semiconductor, Inc |
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52 / 204 page  i.MX53xD Applications Processors for Consumer Products, Rev. 2 52 Freescale Semiconductor Electrical Characteristics Table 36. NFC—Timing Characteristics ID Parameter Symbol Asymmetric Mode Min Symmetric Mode Min Max NF1 NFCLE setup Time tCLS 2T + 0.1 2T + 0.1 — NF2 NFCLE Hold Time tCLH T – 4.45 T – 4.45 — NF31 1 In case of NUM_OF_DEVICES is greater than 0 (for example, interleaved mode), then only during the data phase of symmetric mode the setup time will equal 1.5T + 0.95. NFCE_B Setup Time tCS 3T + 0.95 3T+0.95 — NF4 NFCE_B Hold Time tCH 2T–5.55 1.5T–5.55 — NF5 NFWE_B Pulse Width tWP T–1.4 0.5T – 1.4 — NF6 NFALE Setup Time tALS 2T + 0.1 2T + 0.1 — NF7 NFALE Hold Time tALH T – 4.45 T – 4.45 — NF8 Data Setup Time tDS T–0.9 0.5T – 0.9 — NF9 Data Hold Time tDH T – 5.55 0.5T – 5.55 — NF10 Write Cycle Time tWC 2T T–0.5 — NF11 NFWE_B Hold Time tWH T – 1.15 0.5T – 1.15 — NF12 Ready to NFRE_B Low tRR 9T + 8.9 9T + 8.9 — NF13 NFRE_B Pulse Width tRP 1.5T 0.5T–1 — NF14 READ Cycle Time tRC 2T T — NF15 NFRE_B High Hold Time tREH 0.5T – 1.15 0.5T – 1.15 — NF162 2 tDSR is calculated by the following formula: Asymmetric mode: tDSR = tREpd + tDpd + 1/ 2T – Tdl 2 Symmetric mode: tDSR = tREpd + tDpd – Tdl2 tREpd + tDpd = 11.2 ns (including clock skew) where tREpd is RE propogation delay in the chip including I/O pad delay, and tDpd is Data propogation delay from I/O pad to EXTMC including I/O pad delay. tDSR can be used to determine tREA max parameter with the following formula: tREA = 1.5T – tDSR. Data Setup on READ tDSR 11.2 + 0.5T – Tdl3 3 Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (Taclk). Default is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. Taclk is “emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz). 11.2 – Tdl2 — NF174 Data Hold on READ tDHR 0— 2Taclk +T NF185 Data Hold on READ tDHR —Tdl2 –11.2 2Taclk +T NF19 CLE to RE delay tCLR 9T 9T — NF20 CE to RE delay tCRE T–3.45 T–3.45 T+0.3 NF21 WE high to RE low tWHR 10.5T 10.5T — NF22 WE high to busy tWB —— 6T |
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