IMX53CEC datasheet(64/204 Pages) FREESCALE

64 / 204 page

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Electrical Characteristics

MAXC

Output max. delay from

internal driving ADDR/control

FFs to chip outputs.

—

MAXC

Output max. delay from CSx

internal driving FFs to CSx

out.

—

MAXDI

DATA MAXIMUM delay from

chip input data to its internal

5—

—

WE43

Input Data Valid to CSx_B

Invalid

MAXCO - MAXCSO + MAXDI

MAXCO -

MAXCSO +

MAXDI

—ns

WE44

CSx_B Invalid to Input Data

invalid

—

WE45

CSx_B Valid to BEy_B Valid

(Write access)

WE12 - WE6 + (WBEA - CSA)

—

3 + (WBEA - CSA)

WE46

BEy_B Invalid to CSx_B

Invalid (Write access)

WE7 - WE13 + (WBEN -

CSN)

—

-3 + (WBEN - CSN)

MAXD

DTACK MAXIMUM delay from

chip dtack input to its internal

FF + 2 cycles for

synchronization

——

—

WE47

Dtack Active to CSx_B Invalid

MAXCO - MAXCSO +

MAXDTI

MAXCO -

MAXCSO +

MAXDTI

—ns

WE48

CSx_B Invalid to Dtack

invalid

—

1 Parameters WE4... WE21 value see column BCD = 0 in Table 39

2 All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units.

3 CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.

4 CS Negation. This bit field determines when CS signal is negated during read/write cycles.

5 t is axi_clk cycle time.

6 BE Assertion. This bit field determines when BE signal is asserted during read cycles.

7 BE Negation. This bit field determines when BE signal is negated during read cycles.

Table 40. EIM Asynchronous Timing Parameters Table Relative Chip Select

Ref

No.

Parameter

Determination by

Synchronous measured

parameters 12

Min

Max

(If 133 Mhz is

supported by

SOC)

Unit

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