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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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IMX53CEC датащи(PDF) 80 Page - Freescale Semiconductor, Inc |
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IMX53CEC датащи(HTML) 80 Page - Freescale Semiconductor, Inc |
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80 / 204 page  i.MX53xD Applications Processors for Consumer Products, Rev. 2 80 Freescale Semiconductor Electrical Characteristics . Figure 39. MII Transmit Signal Timing Diagram 4.7.5.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL) Table 54 lists MII asynchronous inputs signal timing information. Figure 40 shows MII asynchronous input timings listed in Table 54. . Figure 40. MII Async Inputs Timing Diagram 4.7.5.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC) Table 55 lists MII serial management channel timings. Figure 41 shows MII serial management channel timings listed in Table 55. The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 MII specification. However, the FEC can function correctly with a maximum MDC frequency of 15 MHz. Table 54. MII Async Inputs Signal Timing Num Characteristic 1 1 Test conditions: 25pF on each output signal. Min Max Unit M92 2 FEC_COL has the same timing in 10 Mbit 7-wire interface mode. FEC_CRS to FEC_COL minimum pulse width 1.5 — FEC_TX_CLK period Table 55. MII Transmit Signal Timing ID Characteristics1 Min Max Unit M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) 0 — ns M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay) — 5 ns M12 FEC_MDIO (input) to FEC_MDC rising edge setup 18 — ns FEC_TX_CLK (input) FEC_TXD[3:0] (outputs) FEC_TX_EN FEC_TX_ER M7 M8 M5 M6 FEC_CRS, FEC_COL M9 |
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