IMX53CEC datasheet(28/204 Pages) FREESCALE

28 / 204 page

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Electrical Characteristics

4.2.2

Power-Down Sequence

Power-down sequence should follow one of the following two options:

Option 1: Switch all supplies down simultaneously with further free discharge. A deviation of few

microseconds of actual power-down of the different power rails is acceptable.

Option 2: Switch down supplies, in any order, keeping the following rules:

•

NVCC_CKIH must be powered down at the same time or after the UHVIO IO cell supplies (for

full supply list, refer to Table 7, Ultra High voltage I/O (UHVIO) supplies). A deviation of few

microseconds of actual power-down of the different power rails is acceptable.

•

VDD_REG must be powered down at the same time or after NVCC_EMI_DRAM supply. A

deviation of few microseconds of actual power-down of the different power rails is acceptable.

•

If all of the following conditions are met:

—1. VDD_REG is powered down to 0V (Not Hi-Z)

—2. VDD_DIG_PLL and VDD_ANA_PLL are provided externally,

—3. VDD_REG is powered down before VDD_DIG_PLL and VDD_ANA_PLL

Then the following rule should be kept: VDD_REG output impedance must be higher than 1 k

Ω,

when inactive.

4.2.3

Power Supplies Usage

•

All IO pins should not be externally driven while the IO power supply for the pin (NVCC_xxx) is

off. This can cause internal latch-up and malfunctions due to reverse current flows. For information

about IO power supply of each pin refer to “Power Rail” columns in pin list tables of Section 6,

“Package Information and Contact Assignments.”

•

If not using SATA interface and the embedded thermal sensor, the VP and VPH should be

grounded. In particular, keeping VPH turned OFF while the VP is powered ON is not

recommended and might lead to excessive power consumption.

•

When internal clock source is used for SATA temperature monitor the USB_PHY supplies and

PLL need to be active because they are providing the clock.

•

If not using TVE the module, the TVDAC_DHVDD and TVDAC_AHVDDRGB can remain

floating. If only the GPIO pads in TVDAC_AHVDDRGB domain are in use, the supplies can be

set to GPIO pad voltage range (1.65 V to 3.1 V).

4.3

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

•

General Purpose I/O (GPIO)

•

Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes

•

Low Voltage I/O (LVIO)

•

Ultra High Voltage I/O (UHVIO)

•LVDS I/O

IMX53CEC датащи(PDF) 28 Page - Freescale Semiconductor, Inc

IMX53CEC датащи(HTML) 28 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL