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PIC32MX795F512LT-80I/PF датащи(PDF) 139 Page - Microchip Technology |
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PIC32MX795F512LT-80I/PF датащи(HTML) 139 Page - Microchip Technology |
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139 / 256 page ![]() © 2009-2011 Microchip Technology Inc. DS61156G-page 139 PIC32MX5XX/6XX/7XX 15.0 INPUT CAPTURE The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The Input Capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. The following events cause capture events: 1. Simple capture event modes - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin 2. Capture timer value on every edge (rising and falling) 3. Capture timer value on every edge (rising and falling), specified edge first. 4. Prescaler capture event modes - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base, or two 16-bit timers (Timer2 and Timer3) together to form a 32-bit timer. The selected timer can use either an internal or external clock. Other operational features include: • Device wake-up from capture pin during CPU Sleep and Idle modes • Interrupt on input capture event • 4-word FIFO buffer for capture values Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled • Input capture can also be used to provide additional sources of external interrupts FIGURE 15-1: INPUT CAPTURE BLOCK DIAGRAM Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. “Input Capture” (DS61122) of the “PIC32 Family Reference Manual” , which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. Prescaler 1, 4, 16 Edge Detect FIFO Control Interrupt Event Generation ICxBUF<31:16> Interrupt Timer3 Timer2 ICxCON ICI<1:0> ICx Input 0 1 ICxBUF<15:0> Data Space Interface Peripheral Data Bus C32 ICTMR ICM<2:0> FEDGE ICBNE ICOV ICM<2:0> |
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