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PIC32MX795F512LT-80I/PF датащи(PDF) 143 Page - Microchip Technology |
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PIC32MX795F512LT-80I/PF датащи(HTML) 143 Page - Microchip Technology |
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143 / 256 page ![]() © 2009-2011 Microchip Technology Inc. DS61156G-page 143 PIC32MX5XX/6XX/7XX 17.0 SERIAL PERIPHERAL INTERFACE (SPI) The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, dis- play drivers, Analog-to-Digital Converters, etc. The PIC32 SPI module is compatible with Motorola® SPI and SIOP interfaces. Following are some of the key features of this module: • Master and Slave modes support • Four different clock formats • Enhanced Framed SPI protocol support • User-configurable 8-bit, 16-bit and 32-bit data width • Separate SPI FIFO buffers for receive and transmit - FIFO buffers act as 4/8/16-level deep FIFOs based on 32/16/8-bit data width • Programmable interrupt event on every 8-bit, 16-bit and 32-bit data transfer • Operation during CPU Sleep and Idle mode • Fast bit manipulation using CLR, SET and INV registers FIGURE 17-1: SPI MODULE BLOCK DIAGRAM Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. “Serial Peripheral Interface (SPI)” (DS61106) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. Internal Data Bus SDIx SDOx SSx/FSYNC SCKx SPIxSR bit 0 Shift Control Edge Select Enable Master Clock Baud Rate Slave Select Sync Control Clock Control Transmit Receive and Frame Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register. FIFOs Share Address SPIxBUF SPIxBUF Generator PBCLK Write Read SPIxTXB FIFO SPIxRXB FIFO |
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