PIC32MX795F512LT-80ISLASHPF datasheet(65/256 Pages) MICROCHIP

65 / 256 page

TABLE 4-3:

INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND

PIC32MX695F512H DEVICES(1)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

1000

INTCON

31:16

—

SS0

0000

15:0

—FRZ

—

MVEC

—TPC<2:0>

—

INT4EP

INT3EP

INT2EP

INT1EP

INT0EP

0000

1010 INTSTAT(3)

31:16

—

0000

15:0

—

SRIPL<2:0>

—

VEC<5:0>

0000

1020

IPTMR

31:16

IPTMR<31:0>

0000

15:0

0000

1030

IFS0

I2C1MIF

I2C1SIF

I2C1BIF

U1TXIF

U1RXIF

U1EIF

—

OC5IF

IC5IF

T5IF

INT4IF

OC4IF

IC4IF

T4IF

0000

31:16

SPI3TXIF SPI3RXIF

SPI3EIF

I2C3MIF

I2C3SIF

I2C3BIF

15:0

INT3IF

OC3IF

IC3IF

T3IF

INT2IF

OC2IF

IC2IF

T2IF

INT1IF

OC1IF

IC1IF

T1IF

INT0IF

CS1IF

CS0IF

CTIF

0000

1040

IFS1

31:16

IC3EIF

IC2EIF

IC1EIF

ETHIF

—

USBIF

FCEIF

DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2)

DMA3IF

DMA2IF

DMA1IF

DMA0IF

0000

RTCCIF

FSCMIF

—

U2TXIF

U2RXIF

U2EIF

U3TXIF

U3RXIF

U3EIF

CMP2IF

CMP1IF

PMPIF

AD1IF

CNIF

0000

15:0

SPI4TXIF SPI4RXIF

SPI4EIF

SPI2TXIF SPI2RXIF

SPI2EIF

I2C5MIF

I2C5SIF

I2C5BIF

I2C4MIF

I2C4SIF

I2C4BIF

1050

IFS2

31:16

—

0000

15:0

—

U5TXIF

U5RXIF

U5EIF

U6TXIF

U6RXIF

U6EIF

U4TXIF

U4RXIF

U4EIF

PMPEIF

IC5EIF

IC4EIF

0000

1060

IEC0

I2C1MIE

I2C1SIE

I2C1BIE

U1TXIE

U1RXIE

U1EIE

—

OC5IE

IC5IE

T5IE

INT4IE

OC4IE

IC4IE

T4IE

0000

31:16

SPI3TXIE SPI3RXIE

SPI3EIE

I2C3MIE

I2C3SIE

I2C3BIE

15:0

INT3IE

OC3IE

IC3IE

T3IE

INT2IE

OC2IE

IC2IE

T2IE

INT1IE

OC1IE

IC1IE

T1IE

INT0IE

CS1IE

CS0IE

CTIE

0000

1070

IEC1

31:16

IC3EIE

IC2EIE

IC1EIE

ETHIE

—

USBIE

FCEIE

DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2)

DMA3IE

DMA2IE

DMA1IE

DMA0IE

0000

RTCCIE

FSCMIE

—

U2TXIE

U2RXIE

U2EIE

U3TXIE

U3RXIE

U3EIE

CMP2IE

CMP1IE

PMPIE

AD1IE

CNIE

0000

15:0

SPI4TXIE SPI4RXIE

SPI4EIE

SPI2TXIE SPI2RXIE

SPI2EIE

I2C5MIE

I2C5SIE

I2C5BIE

I2C4MIE

I2C4SIE

I2C4BIE

1080

IEC2

31:16

—

0000

15:0

—

U5TXIE

U5RXIE

U5EIE

U6TXIE

U6RXIE

U6EIE

U4TXIE

U4RXIE

U4EIE

PMPEIE

IC5EIE

IC4EIE

0000

1090

IPC0

31:16

—

INT0IP<2:0>

INT0IS<1:0>

—

CS1IP<2:0>

CS1IS<1:0>

0000

15:0

—

CS0IP<2:0>

CS0IS<1:0>

—

CTIP<2:0>

CTIS<1:0>

0000

10A0

IPC1

31:16

—

INT1IP<2:0>

INT1IS<1:0>

—

OC1IP<2:0>

OC1IS<1:0>

0000

15:0

—

IC1IP<2:0>

IC1IS<1:0>

—

T1IP<2:0>

T1IS<1:0>

0000

10B0

IPC2

31:16

—

INT2IP<2:0>

INT2IS<1:0>

—

OC2IP<2:0>

OC2IS<1:0>

0000

15:0

—

IC2IP<2:0>

IC2IS<1:0>

—

T2IP<2:0>

T2IS<1:0>

0000

10C0

IPC3

31:16

—

INT3IP<2:0>

INT3IS<1:0>

—

OC3IP<2:0>

OC3IS<1:0>

0000

15:0

—

IC3IP<2:0>

IC3IS<1:0>

—

T3IP<2:0>

T3IS<1:0>

0000

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV

Registers” for more information.

These bits are not available on PIC32MX664 devices.

This register does not have associated CLR, SET, and INV registers.

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