| поискавой системы для электроныых деталей |
|
PIC32MX795F512LT-80I/PF датащи(PDF) 40 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC32MX795F512LT-80I/PF датащи(HTML) 40 Page - Microchip Technology |
|
40 / 256 page ![]() PIC32MX5XX/6XX/7XX DS61156G-page 40 © 2009-2011 Microchip Technology Inc. EMDC 30 71 C11 O — Ethernet management data clock(2) EMDIO 49 68 E9 I/O — Ethernet management data(2) AERXD0 43 18 G1 I ST Alternate Ethernet Receive Data 0(2) AERXD1 42 19 G2 I ST Alternate Ethernet Receive Data 1(2) AERXD2 — 28 L2 I ST Alternate Ethernet Receive Data 2(2) AERXD3 — 29 K3 I ST Alternate Ethernet Receive Data 3(2) AERXERR 55 1 B2 I ST Alternate Ethernet receive error input(2) AERXDV — 12 F2 I ST Alternate Ethernet receive data valid(2) AECRSDV 44 12 F2 I ST Alternate Ethernet carrier sense data valid(2) AERXCLK — 14 F3 I ST Alternate Ethernet receive clock(2) AEREFCLK 45 14 F3 I ST Alternate Ethernet reference clock(2) AETXD0 59 47 L9 O — Alternate Ethernet Transmit Data 0(2) AETXD1 58 48 K9 O — Alternate Ethernet Transmit Data 1(2) AETXD2 — 44 L8 O — Alternate Ethernet Transmit Data 2(2) AETXD3 — 43 K7 O — Alternate Ethernet Transmit Data 3(2) AETXERR — 35 J5 O — Alternate Ethernet transmit error(2) AETXEN 54 67 E8 O — Alternate Ethernet transmit enable(2) AETXCLK — 66 E11 I ST Alternate Ethernet transmit clock(2) AECOL — 42 L7 I ST Alternate Ethernet collision detect(2) AECRS — 41 J7 I ST Alternate Ethernet carrier sense(2) AEMDC 30 71 C11 O — Alternate Ethernet Management Data clock(2) AEMDIO 49 68 E9 I/O — Alternate Ethernet Management Data(2) TRCLK — 91 C5 O — Trace clock TRD0 — 97 A3 O — Trace Data bits 0-3 TRD1 — 96 C3 O — TRD2 — 95 C4 O — TRD3 — 92 B5 O — PGED1 16 25 K2 I/O ST Data I/O pin for Programming/Debugging Communication Channel 1 PGEC1 15 24 K1 I ST Clock input pin for Programming/Debugging Communication Channel 1 PGED2 18 27 J3 I/O ST Data I/O pin for Programming/Debugging Communication Channel 2 PGEC2 17 26 L1 I ST Clock input pin for Programming/Debugging Communication Channel 2 MCLR 7 13 F1 I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device. TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number(1) Pin Type Buffer Type Description 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |