PIC32MX795F512LT-80ISLASHPF datasheet(53/256 Pages) MICROCHIP

53 / 256 page

DS61156G-page 53

PIC32MX5XX/6XX/7XX

Coprocessor 0 also contains the logic for identifying

and managing exceptions. Exceptions can be caused

by a variety of sources, including alignment errors in

data, external events or program errors. Table 3-3 lists

the exception types in order of priority.

TABLE 3-3:

PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES

Exception

Description

Reset

Assertion MCLR or a Power-on Reset (POR).

DSS

EJTAG debug single step.

DINT

EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the

EjtagBrk bit in the ECR register.

NMI

Assertion of NMI signal.

Interrupt

Assertion of unmasked hardware or software interrupt signal.

DIB

EJTAG debug hardware instruction break matched.

AdEL

Fetch address alignment error.

Fetch reference to protected address.

IBE

Instruction fetch bus error.

DBp

EJTAG breakpoint (execution of SDBBP instruction).

Sys

Execution of SYSCALL instruction.

Execution of BREAK instruction.

Execution of a reserved instruction.

CpU

Execution of a coprocessor instruction for a coprocessor that is not enabled.

CEU

Execution of a CorExtend instruction when CorExtend is not enabled.

Execution of an arithmetic instruction that overflowed.

Execution of a trap (when trap condition is true).

DDBL/DDBS

EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).

AdEL

Load address alignment error.

Load reference to protected address.

AdES

Store address alignment error.

Store to protected address.

DBE

Load or store bus error.

DDBL

EJTAG data hardware breakpoint matched in load data compare.

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