PIC32MX795F512LT-80ISLASHPF datasheet(91/256 Pages) MICROCHIP

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33B0 DCH4SSIZ

31:16

—

0000

15:0

CHSSIZ15:0>

0000

33C0 DCH4DSIZ

31:16

—

0000

15:0

CHDSIZ<15:0>

0000

33D0 DCH4SPTR

31:16

—

0000

15:0

CHSPTR<15:0>

0000

33E0 DCH4DPTR

31:16

—

0000

15:0

CHDPTR<15:0>

0000

33F0 DCH4CSIZ

31:16

—

0000

15:0

CHCSIZ<15:0>

0000

3400 DCH4CPTR

31:16

—

0000

15:0

CHCPTR<15:0>

0000

3410 DCH4DAT

31:16

—

0000

15:0

—

CHPDAT<7:0>

0000

3420 DCH5CON

31:16

—

0000

15:0

CHBUSY

—

CHCHNS

CHEN

CHAED

CHCHN

CHAEN

—

CHEDET

CHPRI<1:0>

0000

3430 DCH5ECON

31:16

—

CHAIRQ<7:0>

00FF

15:0

CHSIRQ<7:0>

CFORCE

CABORT

PATEN

SIRQEN

AIRQEN

—

FF00

3440

DCH5INT

31:16

—

CHSDIE

CHSHIE

CHDDIE

CHDHIE

CHBCIE

CHCCIE

CHTAIE

CHERIE 0000

15:0

—

CHSDIF

CHSHIF

CHDDIF

CHDHIF

CHBCIF

CHCCIF

CHTAIF

CHERIF 0000

3450 DCH5SSA

31:16

CHSSA<31:0>

0000

15:0

0000

3460 DCH5DSA

31:16

CHDSA<31:0>

0000

15:0

0000

3470 DCH5SSIZ

31:16

—

0000

15:0

CHSSIZ<15:0>

0000

3480 DCH5DSIZ

31:16

—

0000

15:0

CHDSIZ<15:0>

0000

3490 DCH5SPTR

31:16

—

0000

15:0

CHSPTR<15:0>

0000

34A0 DCH5DPTR

31:16

—

0000

15:0

CHDPTR<15:0>

0000

34B0 DCH5CSIZ

31:16

—

0000

15:0

CHCSIZ<15:0>

0000

34C0 DCH5CPTR

31:16

—

0000

15:0

CHCPTR<15:0>

0000

TABLE 4-19:

DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more

information.

DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.

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