PIC32MX795F512LT-80ISLASHPF datasheet(75/256 Pages) MICROCHIP

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TABLE 4-8:

TIMER1-TIMER5 REGISTER MAP(1)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

0600 T1CON

31:16

—

0000

15:0

FRZ

SIDL

TWDIS

TWIP

—

—TGATE

—

TCKPS<1:0>

—

TSYNC

TCS

—

0000

0610

TMR1

31:16

—

0000

15:0

TMR1<15:0>

0000

0620

PR1

31:16

—

0000

15:0

PR1<15:0>

FFFF

0800 T2CON

31:16

—

0000

15:0

FRZ

SIDL

—

TGATE

TCKPS<2:0>

T32

—TCS(2)

—

0000

0810

TMR2

31:16

—

0000

15:0

TMR2<15:0>

0000

0820

PR2

31:16

—

0000

15:0

PR2<15:0>

FFFF

0A00 T3CON

31:16

—

0000

15:0

FRZ

SIDL

—

TGATE

TCKPS<2:0>

—

—TCS(2)

—

0000

0A10

TMR3

31:16

—

0000

15:0

TMR3<15:0>

0000

0A20

PR3

31:16

—

0000

15:0

PR3<15:0>

FFFF

0C00 T4CON

31:16

—

0000

15:0

FRZ

SIDL

—

TGATE

TCKPS<2:0>

T32

—TCS(2)

—

0000

0C10

TMR4

31:16

—

0000

15:0

TMR4<15:0>

0000

0C20

PR4

31:16

—

0000

15:0

PR4<15:0>

FFFF

0E00 T5CON

31:16

—

0000

15:0

FRZ

SIDL

—

TGATE

TCKPS<2:0>

—

—TCS(2)

—

0000

0E10

TMR5

31:16

—

0000

15:0

TMR5<15:0>

0000

0E20

PR5

31:16

—

0000

15:0

PR5<15:0>

FFFF

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more

information.

These bits are not available on 64-pin devices.

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