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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC32MX795F512LT-80I/PF датащи(PDF) 39 Page - Microchip Technology |
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PIC32MX795F512LT-80I/PF датащи(HTML) 39 Page - Microchip Technology |
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39 / 256 page  © 2009-2011 Microchip Technology Inc. DS61156G-page 39 PIC32MX5XX/6XX/7XX PMALL 30 44 L8 O — Parallel Master Port address latch enable low byte (Multiplexed Master modes) PMALH 29 43 K7 O — Parallel Master Port address latch enable high byte (Multiplexed Master modes) PMRD 53 82 B8 O — Parallel Master Port read strobe PMWR 52 81 C8 O — Parallel Master Port write strobe VBUS 34 54 H8 I Analog USB bus power monitor VUSB 35 55 H9 P — USB internal transceiver supply. If the USB module is not used, this pin must be connected to VDD. VBUSON 11 20 H1 O — USB Host and OTG bus power control output D+ 37 57 H10 I/O Analog USB D+ D- 36 56 J11 I/O Analog USB D- USBID 33 51 K10 I ST USB OTG ID detect C1RX 58 87 B6 I ST CAN1 bus receive pin C1TX 59 88 A6 O — CAN1 bus transmit pin AC1RX 32 40 K6 I ST Alternate CAN1 bus receive pin AC1TX 31 39 L6 O — Alternate CAN1 bus transmit pin C2RX 29 90 A5 I ST CAN2 bus receive pin C2TX 21 89 E6 O — CAN2 bus transmit pin AC2RX — 8 E2 1 ST Alternate CAN2 bus receive pin AC2TX — 7 E4 O — Alternate CAN2 bus transmit pin ERXD0 61 41 J7 I ST Ethernet Receive Data 0(2) ERXD1 60 42 L7 I ST Ethernet Receive Data 1(2) ERXD2 59 43 K7 I ST Ethernet Receive Data 2(2) ERXD3 58 44 L8 I ST Ethernet Receive Data 3(2) ERXERR 64 35 J5 I ST Ethernet receive error input(2) ERXDV 62 12 F2 I ST Ethernet receive data valid(2) ECRSDV 62 12 F2 I ST Ethernet carrier sense data valid(2) ERXCLK 63 14 F3 I ST Ethernet receive clock(2) EREFCLK 63 14 F3 I ST Ethernet reference clock(2) ETXD0 2 88 A6 O — Ethernet Transmit Data 0(2) ETXD1 3 87 B6 O — Ethernet Transmit Data 1(2) ETXD2 43 79 A9 O — Ethernet Transmit Data 2(2) ETXD3 42 80 D8 O — Ethernet Transmit Data 3(2) ETXERR 54 89 E6 O — Ethernet transmit error(2) ETXEN 1 83 D7 O — Ethernet transmit enable(2) ETXCLK 55 84 C7 I ST Ethernet transmit clock(2) ECOL 44 10 E3 I ST Ethernet collision detect(2) ECRS 45 11 F4 I ST Ethernet carrier sense(2) TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number(1) Pin Type Buffer Type Description 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. |
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