PIC32MX795F512LT-80ISLASHPF datasheet(133/256 Pages) MICROCHIP

133 / 256 page

DS61156G-page 133

PIC32MX5XX/6XX/7XX

12.0 I/O PORTS

General purpose I/O pins are the simplest of peripher-

als. They allow the PIC® MCU to monitor and control

other devices. To add flexibility and functionality, some

pins are multiplexed with alternate function(s). These

functions depend on which peripheral features are on

the device. In general, when a peripheral is functioning,

that pin may not be used as a general purpose I/O pin.

Following are some of the key features of this module:

• Individual output pin open-drain enable/disable

• Individual input pin weak pull-up enable/disable

• Monitor selective inputs and generate interrupt

when change in pin state is detected

• Operation during CPU Sleep and Idle modes

• Fast bit manipulation using CLR, SET and INV

registers

Figure 12-1 illustrates a block diagram of a typical

multiplexed I/O port.

FIGURE 12-1:

BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE

Note 1:

This data sheet summarizes the features

of the PIC32MX5XX/6XX/7XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 12. “I/O Ports”

(DS61120)

the

“PIC32

Family

Reference Manual”

, which is available

from

the

Microchip

web

site

(www.microchip.com/PIC32).

Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization”

this data sheet for device-specific register

and bit information.

Peripheral Output Data

Peripheral Module

Peripheral Output Enable

PIO Module

Peripheral Module Enable

WR LAT

I/O Pin

WR PORT

Data Bus

RD LAT

RD PORT

RD TRIS

WR TRIS

RD ODC

SYSCLK

EN Q

SYSCLK

WR ODC

ODC

TRIS

LAT

Sleep

Output Multiplexers

I/O Cell

Synchronization

Peripheral Input

Legend:

R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.

Note:

This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure

for any specific port/peripheral combination may be different than it is shown here.

Peripheral Input Buffer

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