PIC32MX795F512LT-80ISLASHPF datasheet(129/256 Pages) MICROCHIP

129 / 256 page

DS61156G-page 129

PIC32MX5XX/6XX/7XX

10.0 DIRECT MEMORY ACCESS

(DMA) CONTROLLER

The PIC32 Direct Memory Access (DMA) controller is a

bus master module useful for data transfers between

different devices without CPU intervention. The source

and destination of a DMA transfer can be any of the

memory mapped modules existent in the PIC32 (such

as Peripheral Bus (PBUS) devices: SPI, UART, PMP,

etc.) or memory itself.

Following are some of the key features of the DMA

controller module:

• Four identical channels, each featuring:

- Auto-increment source and destination

address registers

- Source and destination pointers

- Memory to memory and memory to

peripheral transfers

• Automatic word-size detection:

- Transfer granularity, down to byte level

- Bytes need not be word-aligned at source

and destination

• Fixed priority channel arbitration

• Flexible DMA channel operating modes:

- Manual (software) or automatic (interrupt)

DMA requests

- One-Shot or Auto-Repeat Block Transfer

modes

- Channel-to-channel chaining

• Flexible DMA requests:

- A DMA request can be selected from any of

the peripheral interrupt sources

- Each channel can select any (appropriate)

observable interrupt as its DMA request

source

- A DMA transfer abort can be selected from

any of the peripheral interrupt sources

- Pattern (data) match transfer termination

• Multiple DMA channel status interrupts:

- DMA channel block transfer complete

- Source empty or half empty

- Destination full or half full

- DMA transfer aborted due to an external

event

- Invalid DMA address generated

• DMA debug support features:

- Most recent address accessed by a DMA

channel

- Most recent DMA channel to transfer data

• CRC Generation module:

- CRC module can be assigned to any of the

available channels

- CRC module is highly configurable

FIGURE 10-1:

DMA BLOCK DIAGRAM

Note 1:

This data sheet summarizes the features

of the PIC32MX5XX/6XX/7XX family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 31. “Direct

Memory Access (DMA) Controller”

(DS61117)

the

“PIC32

Family

Reference Manual”

, which is available

from

the

Microchip

web

site

(www.microchip.com/PIC32).

Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization”

this data sheet for device-specific register

and bit information.

Address Decoder

Channel 0 Control

Channel 1 Control

Channel n Control

Global Control

(DMACON)

Bus Interface

Channel Priority

Arbitration

SEL

System IRQ

INT Controller

Device Bus + Bus Arbitration

Peripheral Bus

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