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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC32MX795F512LT-80I/PF датащи(PDF) 127 Page - Microchip Technology |
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PIC32MX795F512LT-80I/PF датащи(HTML) 127 Page - Microchip Technology |
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127 / 256 page  © 2009-2011 Microchip Technology Inc. DS61156G-page 127 PIC32MX5XX/6XX/7XX 9.0 PREFETCH CACHE Prefetch cache increases performance for applications executing out of the cacheable program Flash memory regions by implementing instruction caching, constant data caching and instruction prefetching. 9.1 Features • 16 fully associative lockable cache lines • 16-byte cache lines • Up to four cache lines allocated to data • Two cache lines with address mask to hold repeated instructions • Pseudo LRU replacement policy • All cache lines are software writable • 16-byte parallel memory fetch • Predictive instruction prefetch A simplified block diagram of the Prefetch Cache module is illustrated in Figure 9-1. FIGURE 9-1: PREFETCH CACHE MODULE BLOCK DIAGRAM Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Prefetch Cache” (DS61119) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. Hit Logic Tag Logic Cache Line Cache Line Address Encode FSM Bus Ctrl Cache Ctrl Prefetch Ctrl Hit LRU Miss LRU RDATA CTRL CTRL PFM PreFetch PreFetch Tag Pre-Fetch Pre-Fetch Prefetch Prefetch |
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