AD9522-5SLASHPCBZ datasheet(69/76 Pages) AD

69 / 76 page

AD9522-5

Rev. 0 | Page 69 of 76

Reg.

Addr

(Hex) Bit(s) Name

Description

0FC

[2]

CSDLD En OUT2 OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FC

[1]

CSDLD En OUT1 OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FC

[0]

CSDLD En OUT0 OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FD

[3]

CSDLD En

OUT11

OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FD

[2]

CSDLD En

OUT10

OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FD

[1]

CSDLD En OUT9 OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FD

[0]

CSDLD En OUT8 OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

Table 49. LVDS Channel Dividers

Reg.

Addr

(Hex) Bit(s) Name

Description

190

[7:4]

Divider 0 low cycles

Number of clock cycles (minus 1) of the divider input during which the divider output stays

low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7).

190

[3:0]

Divider 0 high cycles

Number of clock cycles (minus 1) of the divider input during which the divider output stays

high. A value of 0x7 means the divider is high for eight input clock cycles (default: 0x7).

191

[7]

Divider 0 bypass

Bypasses and powers down the divider; routes input to divider output.

[7] = 0; use divider (default).

[7] = 1; bypass divider.

191

[6]

Divider 0 ignore SYNC

Ignore SYNC.

[6] = 0; obey chip-level SYNC signal (default).

[6] = 1; ignore chip-level SYNC signal.

191

[5]

Divider 0 force high

Forces divider output to high. This requires that ignore SYNC also be set.

[5] = 0; divider output forced to low (default).

[5] = 1; divider output forced to high.

191

[4]

Divider 0 start high

Selects clock output to start high or start low.

[4] = 0; start low (default).

[4] = 1; start high.

191

[3:0]

Divider 0 phase offset

Phase offset (default: 0x0).

192

[2]

Channel 0 power-down

Channel 0 powers down.

[2] = 0; normal operation (default).

[2] = 1; powered down. (OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 are put into the high

impedance power-down mode by setting this bit.)

192

[0]

Disable Divider 0 DCC

Duty-cycle correction function.

[0] = 0; enable duty-cycle correction (default).

[0] = 1; disable duty-cycle correction.

193

[7:4]

Divider 1 low cycles

Number of clock cycles (minus 1) of the divider input during which the divider output stays

low. A value of 0x3 means the divider is low for four input clock cycles (default: 0x3).

193

[3:0]

Divider 1 high cycles

Number of clock cycles (minus 1) of the divider input during which the divider output stays

high. A value of 0x3 means the divider is high for four input clock cycles (default: 0x3).

194

[7]

Divider 1 bypass

Bypasses and powers down the divider; routes input to divider output.

[7] = 0; use divider (default).

[7] = 1; bypass divider.

194

[6]

Divider 1 ignore SYNC

Ignore SYNC.

[6] = 0; obey chip-level SYNC signal (default).

[6] = 1; ignore chip-level SYNC signal.

194

[5]

Divider 1 force high

Forces divider output to high. This requires that ignore SYNC also be set.

[5] = 0; divider output forced to low (default).

[5] = 1; divider output forced to high.

AD9522-5/PCBZ датащи(PDF) 69 Page - Analog Devices

AD9522-5/PCBZ датащи(HTML) 69 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

датащи скачать

ссылки URL