AD9522-5SLASHPCBZ datasheet(68/76 Pages) AD

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AD9522-5

Rev. 0 | Page 68 of 76

Table 48. Output Driver Control

Reg.

Addr

(Hex) Bit(s) Name

Description

0F0

[7]

OUT0 format

Selects the output type for OUT0.

[7] = 0; LVDS (default).

[7] = 1; CMOS.

0F0

[6:5]

OUT0 CMOS

configuration

Sets the CMOS output configuration for OUT0 when 0x0F0[7] = 1.

[6:5]

OUT0A

OUT0B

Tristate

11 (default)

0F0

[4:3]

OUT0 polarity

Sets the output polarity for OUT0.

[7]

[4]

[3]

Output Type

OUT0A

OUT0B

0 (default)

LVDS

Noninverting

Inverting

LVDS

Inverting

Noninverting

0 (default)

CMOS

Noninverting

CMOS

Inverting

CMOS

Noninverting

Inverting

CMOS

Inverting

Noninverting

0F0

[2:1]

OUT0 LVDS

differential

voltage

Sets the LVDS output differential voltage (VOD).

[2]

[1]

IOD (mA)

1.75 (VOD = 175 mV for 100 Ω termination across differential pair)

0 (default)

1 (default)

3.5 (VOD = 350 mV for 100 Ω termination across differential pair)

5.25 (VOD = 525 mV for 100 Ω termination across differential pair)

7.0 (VOD = 700 mV for 100 Ω termination across differential pair)

0F0

[0]

OUT0 LVDS

power-down

LVDS power-down.

[0] = 0; normal operation (default).

[0] = 1; power-down. Output driver is in a high impedance state.

0F1

[7:0]

OUT1 control

This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0.

0F2

[7:0]

OUT2 control

This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0.

0F3

[7:0]

OUT3 control

This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0.

0F4

[7:0]

OUT4 control

This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0.

0F5

[7:0]

OUT5 control

This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.

0F6

[7:0]

OUT6 control

This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.

0F7

[7:0]

OUT7 control

This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.

0F8

[7:0]

OUT8 control

This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.

0F9

[7:0]

OUT9 control

This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.

0FA

[7:0]

OUT10 control

This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.

0FB

[7:0]

OUT11 control

This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.

0FC

[7]

CSDLD En OUT7 OUT7 is enabled only if CSDLD is high.

[7]

CSDLD Signal

OUT7 Enable Status

Not affected by CSDLD signal (default).

Asynchronous power-down.

Asynchronously enable OUT7 if not powered down by other settings.

To use this feature, the user must use current source digital lock detect,

and set the enable LD pin comparator bit (0x01D[3]).

0FC

[6]

CSDLD En OUT6 OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FC

[5]

CSDLD En OUT5 OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FC

[4]

CSDLD En OUT4 OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FC

[3]

CSDLD En OUT3 OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

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