AD9522-5SLASHPCBZ datasheet(38/76 Pages) AD

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AD9522-5

Rev. 0 | Page 38 of 76

MODE 1 (CLOCK DISTRIBUTION MODE)

DISTRIBUTION

CLOCK

MODE 2 (HF CLOCK DISTRIBUTION MODE)

CLK

DIVIDE BY 1,

2, 3, 4, 5, OR 6

CLOCK

DISTRI-

BUTION

PLL

CLK

DIVIDE BY 1,

2, 3, 4, 5, OR 6

CLOCK

DISTRI-

BUTION

PLL

DISTRIBUTION

CLOCK

Figure 37. Simplified Diagram of the Two Clock Distribution Operation Modes

CLOCK DISTRIBUTION

A clock channel consists of three LVDS clock outputs or six

CMOS clock outputs that share a common divider. A clock

output consists of the drivers that connect to the output pins.

The clock outputs have either LVDS or CMOS at the pins.

The AD9522 has four clock channels. Each channel has its own

programmable divider that divides the clock frequency applied

to its input. The channel dividers can divide by any integer

from 1 to 32.

The AD9522 features a VCO divider that divides the VCO output

by 1, 2, 3, 4, 5, or 6 before going to the individual channel dividers.

The VCO divider has two purposes. The first is to limit the

maximum input frequency of the channel dividers to 1.6 GHz.

The other is to allow the AD9522 to generate even lower

frequencies than would be possible with only a simple post divider.

The channel dividers allow for a selection of various duty cycles,

depending on the currently set division. That is, for any specific

division, D, the output of the divider can be set to high for N + 1

input clock cycles and low for M + 1 input clock cycles (where

D = N + M + 2). For example, a divide-by-5 can be high for one

divider input cycle and low for four cycles, or a divide-by-5 can

be high for three divider input cycles and low for two cycles.

Other combinations are also possible.

The channel dividers include a duty-cycle correction function

that can be disabled. In contrast to the selectable duty cycle

just described, this function can correct a non-50% duty cycle

caused by an odd division. However, this requires that the

division be set by M = N + 1.

In addition, the channel dividers allow a coarse phase offset or

delay to be set. Depending on the division selected, the output

can be delayed by up to 15 input clock cycles. For example, if

the frequency at the input of the channel divider is 1 GHz, the

channel divider output can be delayed by up to 15 ns. The

divider outputs can also be set to start high or to start low.

Operation Modes

The AD9522-5 has two clock distribution operating modes that

are shown in Figure 37.

It is not necessary to use the VCO divider if the CLK frequency

is less than the maximum channel divider input frequency

(1600 MHz); otherwise, the VCO divider must be used to

reduce the frequency going to the channel dividers.

Table 26 shows how the operation modes are selected. 0x1E1[0]

selects the channel divider source.

Table 26. Operation Modes

Mode

0x1E1[0]

VCO Divider

Used

Not used

Clock Frequency Division

The total frequency division is a combination of the VCO

divider (when used) and the channel divider. When the VCO

divider is used, the total division from the CLK input to the

output is the product of the VCO divider (1, 2, 3, 4, 5, or 6)

and the division of the channel divider. Table 27 indicates how

the frequency division for a channel is set.

Table 27. Frequency Division

VCO Divider

Setting1

Channel Divider

Setting

Resulting Frequency

Division

1 to 6

2 to 32

(1 to 6) × (2 to 32)

2 to 6

Bypass

(2 to 6) × (1)

Bypass

Output static (illegal state)

VCO divider

bypassed

Bypass

VCO divider

bypassed

2 to 32

1 The bypass VCO divider (0x1E1[0] = 1) is not the same as VCO divider = 1.

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