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AD9522-5/PCBZ датащи(PDF) 51 Page - Analog Devices

номер детали AD9522-5/PCBZ
подробное описание детали  12 LVDS/24 CMOS Output Clock Generator
PDF  76 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9522-5/PCBZ датащи(HTML) 51 Page - Analog Devices

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AD9522-5
Rev. 0 | Page 51 of 76
CS
SCLK
SDIO
tHIGH
tLOW
tCLK
tS
tDS
tDH
tC
BIT N
BIT N + 1
Figure 56. Serial Control Port Timing—Write
Table 40. Serial Control Port Timing
Parameter
Description
tDS
Setup time between data and rising edge of SCLK
tDH
Hold time between data and rising edge of SCLK
tCLK
Period of the clock
Setup time between the CS falling edge and SCLK rising edge (start of communication cycle)
tS
Setup time between SCLK rising edge and the CS rising edge (end of communication cycle)
tC
tHIGH
Minimum period that SCLK should be in a logic high state
tLOW
Minimum period that SCLK should be in a logic low state
tDV
SCLK to valid SDIO and SDO (see Figure 54)



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