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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9522-5/PCBZ датащи(PDF) 5 Page - Analog Devices |
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AD9522-5/PCBZ датащи(HTML) 5 Page - Analog Devices |
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5 / 76 page  AD9522-5 Rev. 0 | Page 5 of 76 Parameter Min Typ Max Unit Test Conditions/Comments CHARGE PUMP (CP) ICP Sink/Source Programmable High Value 4.8 mA With CPRSET = 5.1 kΩ; higher ICP is possible by changing CPRSET Low Value 0.60 mA With CPRSET = 5.1 kΩ; lower ICP is possible by changing CPRSET Absolute Accuracy 2.5 % Charge pump voltage set to VCP/2 CPRSET Range 2.7 10 kΩ ICP High Impedance Mode Leakage 1 nA Sink-and-Source Current Matching 1 % 0.5 V < VCP < VCP − 0.5 V; VCP is the voltage on the CP (charge pump) pin; VCP is the voltage on the VCP power supply pin ICP vs. VCP 1.5 % 0.5 V < VCP < VCP − 0.5 V ICP vs. Temperature 2 % VCP = VCP/2 V PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 1 FD 300 MHz P = 2 FD 600 MHz P = 3 FD 900 MHz P = 2 DM (2/3) 600 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 2400 MHz P = 16 DM (16/17) 3000 MHz P = 32 DM (32/33) 3000 MHz Prescaler Output Frequency 300 MHz A, B counter input frequency (prescaler input frequency divided by P) PLL N DIVIDER DELAY Register 0x019[2:0]; see Table 47 000 Off 001 385 ps 010 504 ps 011 623 ps 100 743 ps 101 866 ps 110 989 ps 111 1112 ps PLL R DIVIDER DELAY Register 0x019[5:3]; see Table 47 000 Off 001 365 ps 010 486 ps 011 608 ps 100 730 ps 101 852 ps 110 976 ps 111 1101 ps PHASE OFFSET IN ZERO DELAY REF refers to REFIN (REF1)/REFIN (REF2) Phase Offset (REF-to-LVDS Clock Output Pins) in Zero Delay Mode 1890 2348 3026 ps When N delay and R delay are bypassed Phase Offset (REF-to-LVDS Clock Output Pins) in Zero Delay Mode 900 1217 1695 ps When N delay = Setting 111 and R delay is bypassed |
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