AD9522-5SLASHPCBZ datasheet(33/76 Pages) AD

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AD9522-5

Rev. 0 | Page 33 of 76

The current source lock detect provides a current of 110 μA when

DLD is true and shorts to ground when DLD is false. If a capacitor

is connected to the LD pin, it charges at a rate determined by the

current source during the DLD true time but is discharged nearly

instantly when DLD is false. By monitoring the voltage at the

LD pin (top of the capacitor), LD = high happens only after the

DLD is true for a sufficiently long time. Any momentary DLD

false resets the charging. By selecting a properly sized capacitor,

it is possible to delay a lock detect indication until the PLL is

stably locked and the lock detect does not chatter.

To use current source digital lock detect, do the following:

•

Place a capacitor to ground on the LD pin

•

Set 0x01A[5:0] = 0x04

•

Enable the LD pin comparator (0x01D[3] = 1)

The LD pin comparator senses the voltage on the LD pin, and the

comparator output can be made available at the REFMON pin

control (0x01B[4:0]) or the STATUS pin control (0x017[7:2]). The

internal LD pin comparator trip point and hysteresis are given in

Table 14. The voltage on the capacitor can also be sensed by an

external comparator connected to the LD pin. In this case,

enabling the on-board LD pin comparator is not necessary.

The user can asynchronously enable individual clock outputs only

when CSDLD is high. To enable this feature, set the appropriate bits

in the enable output on the CSDLD registers (0x0FC and 0x0FD).

AD9522

REFMON

STATUS

VOUT

110µA

DLD

LD PIN

COMPARATOR

Figure 32. Current Source Digital Lock Detect

External VCXO/VCO Clock Input (CLK/CLK)

This differential input is used to drive the AD9522 clock

distribution section. This input can receive up to 2.4 GHz.

The pins are internally self-biased, and the input signal should

be ac-coupled via capacitors.

CLOCK INPUT

STAGE

CLK

5kΩ

2.5kΩ

Figure 33. CLK Equivalent Input Circuit

The CLK/CLK input can be used either as a distribution only

input (with the PLL off), or as a feedback input for an external

VCO/VCXO using the PLL.

Holdover

The AD9522 PLL has a holdover function. Holdover is

implemented by placing the charge pump in a high impedance

state. This function is useful when the PLL reference clock is

lost. Holdover mode allows the external VCO to maintain a

relatively constant frequency even though there is no reference

clock. Without this function, the charge pump is placed into a

constant pump-up or pump-down state, resulting in a large

VCO frequency shift. Because the charge pump is placed in a

high impedance state, any leakage that occurs at the charge

pump output or the VCO tuning node causes a drift of the VCO

frequency. This can be mitigated by using a loop filter that

contains a large capacitive component because this drift is

limited by the current leakage induced slew rate (ILEAK/C) of

the VCO control voltage.

Both a manual holdover mode, using the SYNC pin, and an

automatic holdover mode are provided. To use either function, the

holdover function must be enabled (0x01D[0]).

External/Manual Holdover Mode

A manual holdover mode can be enabled that allows the user to

place the charge pump into a high impedance state when the

SYNC pin is asserted low. This operation is edge sensitive, not

level sensitive. The charge pump enters a high impedance state

immediately. To take the charge pump out of a high impedance

state, take the SYNC pin high. The charge pump then leaves the

high impedance state synchronously with the next PFD rising

edge from the reference clock. This prevents extraneous charge

pump events from occurring during the time between SYNC

going high and the next PFD event. This also means that the

charge pump stays in a high impedance state if there is no

reference clock present.

The B counter (in the N divider) is reset synchronously with the

charge pump leaving the high impedance state on the reference

path PFD event. This helps align the edges out of the R and N

dividers for faster settling of the PLL. Because the prescaler is

not reset, this feature works best when the B and R numbers are

close because this results in a smaller phase difference for the

loop to settle out.

When using this mode, the channel dividers should be set to ignore

the SYNC pin (at least after an initial SYNC event). If the dividers

are not set to ignore the SYNC pin, any time SYNC is taken low

to put the part into holdover, the distribution outputs turn off.

The channel divider ignore SYNC function is found in 0x191[6],

0x194[6], 0x197[6], and 0x19A[6] for Channel Divider 0, Channel

Divider 1, Channel Divider 2, and Channel Divider 3, respectively.

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