SH7014 datasheet(27/754 Pages) RENESAS

27 / 754 page

Rev.5.00 Sep. 27, 2007 Page xxvii of xxxiv

REJ09B0398-0500

11.3

Operation........................................................................................................................... 298

11.3.1 Watchdog Timer Mode ........................................................................................ 298

11.3.2 Interval Timer Mode ............................................................................................ 300

11.3.3 Clearing the Standby Mode.................................................................................. 300

11.3.4 Timing of Setting the Overflow Flag (OVF) ....................................................... 301

11.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 301

11.4

Usage Notes ...................................................................................................................... 302

11.4.1 TCNT Write and Increment Contention............................................................... 302

11.4.2 Changing CKS2 to CKS0 Bit Values................................................................... 302

11.4.3 Changing between Watchdog Timer/Interval Timer Modes................................ 302

11.4.4 System Reset with

WDTOVF.............................................................................. 303

11.4.5 Internal Reset with the Watchdog Timer ............................................................. 303

Section 12 Serial Communication Interface (SCI) .................................................... 305

12.1

Overview........................................................................................................................... 305

12.1.1 Features ................................................................................................................ 305

12.1.2 Block Diagram ..................................................................................................... 306

12.1.3 Pin Configuration................................................................................................. 307

12.1.4 Register Configuration......................................................................................... 307

12.2

Register Descriptions ........................................................................................................ 308

12.2.1 Receive Shift Register (RSR) .............................................................................. 308

12.2.2 Receive Data Register (RDR) .............................................................................. 308

12.2.3 Transmit Shift Register (TSR) ............................................................................. 308

12.2.4 Transmit Data Register (TDR)............................................................................. 309

12.2.5 Serial Mode Register (SMR)................................................................................ 309

12.2.6 Serial Control Register (SCR).............................................................................. 312

12.2.7 Serial Status Register (SSR) ................................................................................ 316

12.2.8 Bit Rate Register (BRR) ...................................................................................... 320

12.3

Operation........................................................................................................................... 331

12.3.1 Overview.............................................................................................................. 331

12.3.2 Operation in Asynchronous Mode ....................................................................... 333

12.3.3 Multiprocessor Communication........................................................................... 343

12.3.4 Clock Synchronous Operation ............................................................................. 351

12.4

SCI Interrupt Sources and the DMAC .............................................................................. 362

12.5

Usage Notes ...................................................................................................................... 363

12.5.1 TDR Write and TDRE Flags................................................................................ 363

12.5.2 Simultaneous Multiple Receive Errors ................................................................ 363

12.5.3 Break Detection and Processing........................................................................... 364

12.5.4 Sending a Break Signal ........................................................................................ 364

SH7014 датащи(PDF) 27 Page - Renesas Technology Corp

SH7014 датащи(HTML) 27 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL